1//===- LoongArchRegisterInfo.cpp - LoongArch Register Information -*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the LoongArch implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "LoongArchRegisterInfo.h"
15#include "LoongArch.h"
16#include "LoongArchInstrInfo.h"
17#include "LoongArchSubtarget.h"
18#include "MCTargetDesc/LoongArchBaseInfo.h"
19#include "MCTargetDesc/LoongArchMCTargetDesc.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/RegisterScavenging.h"
24#include "llvm/CodeGen/TargetFrameLowering.h"
25#include "llvm/CodeGen/TargetInstrInfo.h"
26#include "llvm/Support/ErrorHandling.h"
27
28using namespace llvm;
29
30#define GET_REGINFO_TARGET_DESC
31#include "LoongArchGenRegisterInfo.inc"
32
33LoongArchRegisterInfo::LoongArchRegisterInfo(unsigned HwMode)
34 : LoongArchGenRegisterInfo(LoongArch::R1, /*DwarfFlavour*/ 0,
35 /*EHFlavor*/ 0,
36 /*PC*/ 0, HwMode) {}
37
38const MCPhysReg *
39LoongArchRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
40 auto &Subtarget = MF->getSubtarget<LoongArchSubtarget>();
41
42 if (MF->getFunction().getCallingConv() == CallingConv::GHC)
43 return CSR_NoRegs_SaveList;
44 switch (Subtarget.getTargetABI()) {
45 default:
46 llvm_unreachable("Unrecognized ABI");
47 case LoongArchABI::ABI_ILP32S:
48 case LoongArchABI::ABI_LP64S:
49 return CSR_ILP32S_LP64S_SaveList;
50 case LoongArchABI::ABI_ILP32F:
51 case LoongArchABI::ABI_LP64F:
52 return CSR_ILP32F_LP64F_SaveList;
53 case LoongArchABI::ABI_ILP32D:
54 case LoongArchABI::ABI_LP64D:
55 return CSR_ILP32D_LP64D_SaveList;
56 }
57}
58
59const uint32_t *
60LoongArchRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
61 CallingConv::ID CC) const {
62 auto &Subtarget = MF.getSubtarget<LoongArchSubtarget>();
63
64 if (CC == CallingConv::GHC)
65 return CSR_NoRegs_RegMask;
66 switch (Subtarget.getTargetABI()) {
67 default:
68 llvm_unreachable("Unrecognized ABI");
69 case LoongArchABI::ABI_ILP32S:
70 case LoongArchABI::ABI_LP64S:
71 return CSR_ILP32S_LP64S_RegMask;
72 case LoongArchABI::ABI_ILP32F:
73 case LoongArchABI::ABI_LP64F:
74 return CSR_ILP32F_LP64F_RegMask;
75 case LoongArchABI::ABI_ILP32D:
76 case LoongArchABI::ABI_LP64D:
77 return CSR_ILP32D_LP64D_RegMask;
78 }
79}
80
81const uint32_t *LoongArchRegisterInfo::getNoPreservedMask() const {
82 return CSR_NoRegs_RegMask;
83}
84
85BitVector
86LoongArchRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
87 const LoongArchFrameLowering *TFI = getFrameLowering(MF);
88 BitVector Reserved(getNumRegs());
89
90 // Use markSuperRegs to ensure any register aliases are also reserved
91 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArch::R0); // zero
92 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArch::R2); // tp
93 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArch::R3); // sp
94 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArch::R21); // non-allocatable
95 if (TFI->hasFP(MF))
96 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArch::R22); // fp
97 // Reserve the base register if we need to realign the stack and allocate
98 // variable-sized objects at runtime.
99 if (TFI->hasBP(MF))
100 markSuperRegs(RegisterSet&: Reserved, Reg: LoongArchABI::getBPReg()); // bp
101
102 assert(checkAllSuperRegsMarked(Reserved));
103 return Reserved;
104}
105
106Register
107LoongArchRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
108 const TargetFrameLowering *TFI = getFrameLowering(MF);
109 return TFI->hasFP(MF) ? LoongArch::R22 : LoongArch::R3;
110}
111
112bool LoongArchRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
113 int SPAdj,
114 unsigned FIOperandNum,
115 RegScavenger *RS) const {
116 // TODO: this implementation is a temporary placeholder which does just
117 // enough to allow other aspects of code generation to be tested.
118
119 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
120
121 MachineInstr &MI = *II;
122 assert(MI.getOperand(FIOperandNum + 1).isImm() &&
123 "Unexpected FI-consuming insn");
124
125 MachineBasicBlock &MBB = *MI.getParent();
126 MachineFunction &MF = *MI.getParent()->getParent();
127 MachineRegisterInfo &MRI = MF.getRegInfo();
128 const LoongArchSubtarget &STI = MF.getSubtarget<LoongArchSubtarget>();
129 const LoongArchInstrInfo *TII = STI.getInstrInfo();
130 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
131 DebugLoc DL = MI.getDebugLoc();
132 bool IsLA64 = STI.is64Bit();
133 unsigned MIOpc = MI.getOpcode();
134
135 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
136 Register FrameReg;
137 StackOffset Offset =
138 TFI->getFrameIndexReference(MF, FI: FrameIndex, FrameReg) +
139 StackOffset::getFixed(Fixed: MI.getOperand(i: FIOperandNum + 1).getImm());
140
141 bool FrameRegIsKill = false;
142
143 int FixedOffset = Offset.getFixed();
144 bool OffsetLegal = true;
145
146 // Handle offsets that exceed the immediate range of the instruction.
147 switch (MIOpc) {
148 case LoongArch::VSTELM_B:
149 case LoongArch::XVSTELM_B:
150 OffsetLegal = isInt<8>(x: FixedOffset);
151 break;
152 case LoongArch::VSTELM_H:
153 case LoongArch::XVSTELM_H:
154 OffsetLegal = isShiftedInt<8, 1>(x: FixedOffset);
155 break;
156 case LoongArch::VSTELM_W:
157 case LoongArch::XVSTELM_W:
158 OffsetLegal = isShiftedInt<8, 2>(x: FixedOffset);
159 break;
160 case LoongArch::VSTELM_D:
161 case LoongArch::XVSTELM_D:
162 OffsetLegal = isShiftedInt<8, 3>(x: FixedOffset);
163 break;
164 }
165
166 if (!OffsetLegal && isInt<12>(x: FixedOffset)) {
167 unsigned Addi = IsLA64 ? LoongArch::ADDI_D : LoongArch::ADDI_W;
168
169 // The offset fits in si12 but is not legal for the instruction,
170 // so use only one scratch register instead.
171 Register ScratchReg = MRI.createVirtualRegister(RegClass: &LoongArch::GPRRegClass);
172 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Addi), DestReg: ScratchReg)
173 .addReg(RegNo: FrameReg)
174 .addImm(Val: FixedOffset);
175 Offset = StackOffset::getFixed(Fixed: 0);
176 FrameReg = ScratchReg;
177 FrameRegIsKill = true;
178 }
179
180 if (!isInt<12>(x: FixedOffset)) {
181 unsigned Addi = IsLA64 ? LoongArch::ADDI_D : LoongArch::ADDI_W;
182 unsigned Add = IsLA64 ? LoongArch::ADD_D : LoongArch::ADD_W;
183
184 // The offset won't fit in an immediate, so use a scratch register instead.
185 // Modify Offset and FrameReg appropriately.
186 Register ScratchReg = MRI.createVirtualRegister(RegClass: &LoongArch::GPRRegClass);
187 TII->movImm(MBB, MBBI: II, DL, DstReg: ScratchReg, Val: Offset.getFixed());
188 if (MIOpc == Addi) {
189 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Add), DestReg: MI.getOperand(i: 0).getReg())
190 .addReg(RegNo: FrameReg)
191 .addReg(RegNo: ScratchReg, flags: RegState::Kill);
192 MI.eraseFromParent();
193 return true;
194 }
195 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Add), DestReg: ScratchReg)
196 .addReg(RegNo: FrameReg)
197 .addReg(RegNo: ScratchReg, flags: RegState::Kill);
198 Offset = StackOffset::getFixed(Fixed: 0);
199 FrameReg = ScratchReg;
200 FrameRegIsKill = true;
201 }
202
203 // Spill CFRs.
204 if (MIOpc == LoongArch::PseudoST_CFR) {
205 Register ScratchReg = MRI.createVirtualRegister(RegClass: &LoongArch::GPRRegClass);
206 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: LoongArch::MOVCF2GR), DestReg: ScratchReg)
207 .add(MO: MI.getOperand(i: 0));
208 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: IsLA64 ? LoongArch::ST_D : LoongArch::ST_W))
209 .addReg(RegNo: ScratchReg, flags: RegState::Kill)
210 .addReg(RegNo: FrameReg)
211 .addImm(Val: Offset.getFixed());
212 MI.eraseFromParent();
213 return true;
214 }
215
216 // Reload CFRs.
217 if (MIOpc == LoongArch::PseudoLD_CFR) {
218 Register ScratchReg = MRI.createVirtualRegister(RegClass: &LoongArch::GPRRegClass);
219 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: IsLA64 ? LoongArch::LD_D : LoongArch::LD_W),
220 DestReg: ScratchReg)
221 .addReg(RegNo: FrameReg)
222 .addImm(Val: Offset.getFixed());
223 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: LoongArch::MOVGR2CF))
224 .add(MO: MI.getOperand(i: 0))
225 .addReg(RegNo: ScratchReg, flags: RegState::Kill);
226 MI.eraseFromParent();
227 return true;
228 }
229
230 MI.getOperand(i: FIOperandNum)
231 .ChangeToRegister(Reg: FrameReg, isDef: false, isImp: false, isKill: FrameRegIsKill);
232 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset.getFixed());
233 return false;
234}
235
236bool LoongArchRegisterInfo::canRealignStack(const MachineFunction &MF) const {
237 if (!TargetRegisterInfo::canRealignStack(MF))
238 return false;
239
240 const MachineRegisterInfo *MRI = &MF.getRegInfo();
241 const LoongArchFrameLowering *TFI = getFrameLowering(MF);
242
243 // Stack realignment requires a frame pointer. If we already started
244 // register allocation with frame pointer elimination, it is too late now.
245 if (!MRI->canReserveReg(PhysReg: LoongArch::R22))
246 return false;
247
248 // We may also need a base pointer if there are dynamic allocas or stack
249 // pointer adjustments around calls.
250 if (TFI->hasReservedCallFrame(MF))
251 return true;
252
253 // A base pointer is required and allowed. Check that it isn't too late to
254 // reserve it.
255 return MRI->canReserveReg(PhysReg: LoongArchABI::getBPReg());
256}
257

source code of llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp