1// SPDX-License-Identifier: GPL-2.0-only
2//
3// rt5682s.c -- RT5682I-VS ALSA SoC audio component driver
4//
5// Copyright 2021 Realtek Semiconductor Corp.
6// Author: Derek Fang <derek.fang@realtek.com>
7//
8
9#include <linux/module.h>
10#include <linux/moduleparam.h>
11#include <linux/init.h>
12#include <linux/delay.h>
13#include <linux/pm.h>
14#include <linux/i2c.h>
15#include <linux/platform_device.h>
16#include <linux/spi/spi.h>
17#include <linux/acpi.h>
18#include <linux/gpio/consumer.h>
19#include <linux/mutex.h>
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/jack.h>
24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
27#include <sound/tlv.h>
28#include <sound/rt5682s.h>
29
30#include "rt5682s.h"
31
32#define DEVICE_ID 0x6749
33
34static const struct rt5682s_platform_data i2s_default_platform_data = {
35 .dmic1_data_pin = RT5682S_DMIC1_DATA_GPIO2,
36 .dmic1_clk_pin = RT5682S_DMIC1_CLK_GPIO3,
37 .jd_src = RT5682S_JD1,
38 .dai_clk_names[RT5682S_DAI_WCLK_IDX] = "rt5682-dai-wclk",
39 .dai_clk_names[RT5682S_DAI_BCLK_IDX] = "rt5682-dai-bclk",
40};
41
42static const char *rt5682s_supply_names[RT5682S_NUM_SUPPLIES] = {
43 [RT5682S_SUPPLY_AVDD] = "AVDD",
44 [RT5682S_SUPPLY_MICVDD] = "MICVDD",
45 [RT5682S_SUPPLY_DBVDD] = "DBVDD",
46 [RT5682S_SUPPLY_LDO1_IN] = "LDO1-IN",
47};
48
49static const struct reg_sequence patch_list[] = {
50 {RT5682S_I2C_CTRL, 0x0007},
51 {RT5682S_DIG_IN_CTRL_1, 0x0000},
52 {RT5682S_CHOP_DAC_2, 0x2020},
53 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_2, 0x0101},
54 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_1, 0x80c0},
55 {RT5682S_HP_CALIB_CTRL_9, 0x0002},
56 {RT5682S_DEPOP_1, 0x0000},
57 {RT5682S_HP_CHARGE_PUMP_2, 0x3c15},
58 {RT5682S_DAC1_DIG_VOL, 0xfefe},
59 {RT5682S_SAR_IL_CMD_2, 0xac00},
60 {RT5682S_SAR_IL_CMD_3, 0x024c},
61 {RT5682S_CBJ_CTRL_6, 0x0804},
62};
63
64static void rt5682s_apply_patch_list(struct rt5682s_priv *rt5682s,
65 struct device *dev)
66{
67 int ret;
68
69 ret = regmap_multi_reg_write(map: rt5682s->regmap, regs: patch_list, ARRAY_SIZE(patch_list));
70 if (ret)
71 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
72}
73
74static const struct reg_default rt5682s_reg[] = {
75 {0x0002, 0x8080},
76 {0x0003, 0x0001},
77 {0x0005, 0x0000},
78 {0x0006, 0x0000},
79 {0x0008, 0x8007},
80 {0x000b, 0x0000},
81 {0x000f, 0x4000},
82 {0x0010, 0x4040},
83 {0x0011, 0x0000},
84 {0x0012, 0x0000},
85 {0x0013, 0x1200},
86 {0x0014, 0x200a},
87 {0x0015, 0x0404},
88 {0x0016, 0x0404},
89 {0x0017, 0x05a4},
90 {0x0019, 0xffff},
91 {0x001c, 0x2f2f},
92 {0x001f, 0x0000},
93 {0x0022, 0x5757},
94 {0x0023, 0x0039},
95 {0x0024, 0x000b},
96 {0x0026, 0xc0c4},
97 {0x0029, 0x8080},
98 {0x002a, 0xa0a0},
99 {0x002b, 0x0300},
100 {0x0030, 0x0000},
101 {0x003c, 0x08c0},
102 {0x0044, 0x1818},
103 {0x004b, 0x00c0},
104 {0x004c, 0x0000},
105 {0x004d, 0x0000},
106 {0x0061, 0x00c0},
107 {0x0062, 0x008a},
108 {0x0063, 0x0800},
109 {0x0064, 0x0000},
110 {0x0065, 0x0000},
111 {0x0066, 0x0030},
112 {0x0067, 0x000c},
113 {0x0068, 0x0000},
114 {0x0069, 0x0000},
115 {0x006a, 0x0000},
116 {0x006b, 0x0000},
117 {0x006c, 0x0000},
118 {0x006d, 0x2200},
119 {0x006e, 0x0810},
120 {0x006f, 0xe4de},
121 {0x0070, 0x3320},
122 {0x0071, 0x0000},
123 {0x0073, 0x0000},
124 {0x0074, 0x0000},
125 {0x0075, 0x0002},
126 {0x0076, 0x0001},
127 {0x0079, 0x0000},
128 {0x007a, 0x0000},
129 {0x007b, 0x0000},
130 {0x007c, 0x0100},
131 {0x007e, 0x0000},
132 {0x007f, 0x0000},
133 {0x0080, 0x0000},
134 {0x0083, 0x0000},
135 {0x0084, 0x0000},
136 {0x0085, 0x0000},
137 {0x0086, 0x0005},
138 {0x0087, 0x0000},
139 {0x0088, 0x0000},
140 {0x008c, 0x0003},
141 {0x008e, 0x0060},
142 {0x008f, 0x4da1},
143 {0x0091, 0x1c15},
144 {0x0092, 0x0425},
145 {0x0093, 0x0000},
146 {0x0094, 0x0080},
147 {0x0095, 0x008f},
148 {0x0096, 0x0000},
149 {0x0097, 0x0000},
150 {0x0098, 0x0000},
151 {0x0099, 0x0000},
152 {0x009a, 0x0000},
153 {0x009b, 0x0000},
154 {0x009c, 0x0000},
155 {0x009d, 0x0000},
156 {0x009e, 0x0000},
157 {0x009f, 0x0009},
158 {0x00a0, 0x0000},
159 {0x00a3, 0x0002},
160 {0x00a4, 0x0001},
161 {0x00b6, 0x0000},
162 {0x00b7, 0x0000},
163 {0x00b8, 0x0000},
164 {0x00b9, 0x0002},
165 {0x00be, 0x0000},
166 {0x00c0, 0x0160},
167 {0x00c1, 0x82a0},
168 {0x00c2, 0x0000},
169 {0x00d0, 0x0000},
170 {0x00d2, 0x3300},
171 {0x00d3, 0x2200},
172 {0x00d4, 0x0000},
173 {0x00d9, 0x0000},
174 {0x00da, 0x0000},
175 {0x00db, 0x0000},
176 {0x00dc, 0x00c0},
177 {0x00dd, 0x2220},
178 {0x00de, 0x3131},
179 {0x00df, 0x3131},
180 {0x00e0, 0x3131},
181 {0x00e2, 0x0000},
182 {0x00e3, 0x4000},
183 {0x00e4, 0x0aa0},
184 {0x00e5, 0x3131},
185 {0x00e6, 0x3131},
186 {0x00e7, 0x3131},
187 {0x00e8, 0x3131},
188 {0x00ea, 0xb320},
189 {0x00eb, 0x0000},
190 {0x00f0, 0x0000},
191 {0x00f6, 0x0000},
192 {0x00fa, 0x0000},
193 {0x00fb, 0x0000},
194 {0x00fc, 0x0000},
195 {0x00fd, 0x0000},
196 {0x00fe, 0x10ec},
197 {0x00ff, 0x6749},
198 {0x0100, 0xa000},
199 {0x010b, 0x0066},
200 {0x010c, 0x6666},
201 {0x010d, 0x2202},
202 {0x010e, 0x6666},
203 {0x010f, 0xa800},
204 {0x0110, 0x0006},
205 {0x0111, 0x0460},
206 {0x0112, 0x2000},
207 {0x0113, 0x0200},
208 {0x0117, 0x8000},
209 {0x0118, 0x0303},
210 {0x0125, 0x0020},
211 {0x0132, 0x5026},
212 {0x0136, 0x8000},
213 {0x0139, 0x0005},
214 {0x013a, 0x3030},
215 {0x013b, 0xa000},
216 {0x013c, 0x4110},
217 {0x013f, 0x0000},
218 {0x0145, 0x0022},
219 {0x0146, 0x0000},
220 {0x0147, 0x0000},
221 {0x0148, 0x0000},
222 {0x0156, 0x0022},
223 {0x0157, 0x0303},
224 {0x0158, 0x2222},
225 {0x0159, 0x0000},
226 {0x0160, 0x4ec0},
227 {0x0161, 0x0080},
228 {0x0162, 0x0200},
229 {0x0163, 0x0800},
230 {0x0164, 0x0000},
231 {0x0165, 0x0000},
232 {0x0166, 0x0000},
233 {0x0167, 0x000f},
234 {0x0168, 0x000f},
235 {0x0169, 0x0001},
236 {0x0190, 0x4131},
237 {0x0194, 0x0000},
238 {0x0195, 0x0000},
239 {0x0197, 0x0022},
240 {0x0198, 0x0000},
241 {0x0199, 0x0000},
242 {0x01ac, 0x0000},
243 {0x01ad, 0x0000},
244 {0x01ae, 0x0000},
245 {0x01af, 0x2000},
246 {0x01b0, 0x0000},
247 {0x01b1, 0x0000},
248 {0x01b2, 0x0000},
249 {0x01b3, 0x0017},
250 {0x01b4, 0x004b},
251 {0x01b5, 0x0000},
252 {0x01b6, 0x03e8},
253 {0x01b7, 0x0000},
254 {0x01b8, 0x0000},
255 {0x01b9, 0x0400},
256 {0x01ba, 0xb5b6},
257 {0x01bb, 0x9124},
258 {0x01bc, 0x4924},
259 {0x01bd, 0x0009},
260 {0x01be, 0x0018},
261 {0x01bf, 0x002a},
262 {0x01c0, 0x004c},
263 {0x01c1, 0x0097},
264 {0x01c2, 0x01c3},
265 {0x01c3, 0x03e9},
266 {0x01c4, 0x1389},
267 {0x01c5, 0xc351},
268 {0x01c6, 0x02a0},
269 {0x01c7, 0x0b0f},
270 {0x01c8, 0x402f},
271 {0x01c9, 0x0702},
272 {0x01ca, 0x0000},
273 {0x01cb, 0x0000},
274 {0x01cc, 0x5757},
275 {0x01cd, 0x5757},
276 {0x01ce, 0x5757},
277 {0x01cf, 0x5757},
278 {0x01d0, 0x5757},
279 {0x01d1, 0x5757},
280 {0x01d2, 0x5757},
281 {0x01d3, 0x5757},
282 {0x01d4, 0x5757},
283 {0x01d5, 0x5757},
284 {0x01d6, 0x0000},
285 {0x01d7, 0x0000},
286 {0x01d8, 0x0162},
287 {0x01d9, 0x0007},
288 {0x01da, 0x0000},
289 {0x01db, 0x0004},
290 {0x01dc, 0x0000},
291 {0x01de, 0x7c00},
292 {0x01df, 0x0020},
293 {0x01e0, 0x04c1},
294 {0x01e1, 0x0000},
295 {0x01e2, 0x0000},
296 {0x01e3, 0x0000},
297 {0x01e4, 0x0000},
298 {0x01e5, 0x0000},
299 {0x01e6, 0x0001},
300 {0x01e7, 0x0000},
301 {0x01e8, 0x0000},
302 {0x01eb, 0x0000},
303 {0x01ec, 0x0000},
304 {0x01ed, 0x0000},
305 {0x01ee, 0x0000},
306 {0x01ef, 0x0000},
307 {0x01f0, 0x0000},
308 {0x01f1, 0x0000},
309 {0x01f2, 0x0000},
310 {0x01f3, 0x0000},
311 {0x01f4, 0x0000},
312 {0x0210, 0x6297},
313 {0x0211, 0xa004},
314 {0x0212, 0x0365},
315 {0x0213, 0xf7ff},
316 {0x0214, 0xf24c},
317 {0x0215, 0x0102},
318 {0x0216, 0x00a3},
319 {0x0217, 0x0048},
320 {0x0218, 0xa2c0},
321 {0x0219, 0x0400},
322 {0x021a, 0x00c8},
323 {0x021b, 0x00c0},
324 {0x021c, 0x0000},
325 {0x021d, 0x024c},
326 {0x02fa, 0x0000},
327 {0x02fb, 0x0000},
328 {0x02fc, 0x0000},
329 {0x03fe, 0x0000},
330 {0x03ff, 0x0000},
331 {0x0500, 0x0000},
332 {0x0600, 0x0000},
333 {0x0610, 0x6666},
334 {0x0611, 0xa9aa},
335 {0x0620, 0x6666},
336 {0x0621, 0xa9aa},
337 {0x0630, 0x6666},
338 {0x0631, 0xa9aa},
339 {0x0640, 0x6666},
340 {0x0641, 0xa9aa},
341 {0x07fa, 0x0000},
342 {0x08fa, 0x0000},
343 {0x08fb, 0x0000},
344 {0x0d00, 0x0000},
345 {0x1100, 0x0000},
346 {0x1101, 0x0000},
347 {0x1102, 0x0000},
348 {0x1103, 0x0000},
349 {0x1104, 0x0000},
350 {0x1105, 0x0000},
351 {0x1106, 0x0000},
352 {0x1107, 0x0000},
353 {0x1108, 0x0000},
354 {0x1109, 0x0000},
355 {0x110a, 0x0000},
356 {0x110b, 0x0000},
357 {0x110c, 0x0000},
358 {0x1111, 0x0000},
359 {0x1112, 0x0000},
360 {0x1113, 0x0000},
361 {0x1114, 0x0000},
362 {0x1115, 0x0000},
363 {0x1116, 0x0000},
364 {0x1117, 0x0000},
365 {0x1118, 0x0000},
366 {0x1119, 0x0000},
367 {0x111a, 0x0000},
368 {0x111b, 0x0000},
369 {0x111c, 0x0000},
370 {0x1401, 0x0404},
371 {0x1402, 0x0007},
372 {0x1403, 0x0365},
373 {0x1404, 0x0210},
374 {0x1405, 0x0365},
375 {0x1406, 0x0210},
376 {0x1407, 0x0000},
377 {0x1408, 0x0000},
378 {0x1409, 0x0000},
379 {0x140a, 0x0000},
380 {0x140b, 0x0000},
381 {0x140c, 0x0000},
382 {0x140d, 0x0000},
383 {0x140e, 0x0000},
384 {0x140f, 0x0000},
385 {0x1410, 0x0000},
386 {0x1411, 0x0000},
387 {0x1801, 0x0004},
388 {0x1802, 0x0000},
389 {0x1803, 0x0000},
390 {0x1804, 0x0000},
391 {0x1805, 0x00ff},
392 {0x2c00, 0x0000},
393 {0x3400, 0x0200},
394 {0x3404, 0x0000},
395 {0x3405, 0x0000},
396 {0x3406, 0x0000},
397 {0x3407, 0x0000},
398 {0x3408, 0x0000},
399 {0x3409, 0x0000},
400 {0x340a, 0x0000},
401 {0x340b, 0x0000},
402 {0x340c, 0x0000},
403 {0x340d, 0x0000},
404 {0x340e, 0x0000},
405 {0x340f, 0x0000},
406 {0x3410, 0x0000},
407 {0x3411, 0x0000},
408 {0x3412, 0x0000},
409 {0x3413, 0x0000},
410 {0x3414, 0x0000},
411 {0x3415, 0x0000},
412 {0x3424, 0x0000},
413 {0x3425, 0x0000},
414 {0x3426, 0x0000},
415 {0x3427, 0x0000},
416 {0x3428, 0x0000},
417 {0x3429, 0x0000},
418 {0x342a, 0x0000},
419 {0x342b, 0x0000},
420 {0x342c, 0x0000},
421 {0x342d, 0x0000},
422 {0x342e, 0x0000},
423 {0x342f, 0x0000},
424 {0x3430, 0x0000},
425 {0x3431, 0x0000},
426 {0x3432, 0x0000},
427 {0x3433, 0x0000},
428 {0x3434, 0x0000},
429 {0x3435, 0x0000},
430 {0x3440, 0x6319},
431 {0x3441, 0x3771},
432 {0x3500, 0x0002},
433 {0x3501, 0x5728},
434 {0x3b00, 0x3010},
435 {0x3b01, 0x3300},
436 {0x3b02, 0x2200},
437 {0x3b03, 0x0100},
438};
439
440static bool rt5682s_volatile_register(struct device *dev, unsigned int reg)
441{
442 switch (reg) {
443 case RT5682S_RESET:
444 case RT5682S_CBJ_CTRL_2:
445 case RT5682S_I2S1_F_DIV_CTRL_2:
446 case RT5682S_I2S2_F_DIV_CTRL_2:
447 case RT5682S_INT_ST_1:
448 case RT5682S_GPIO_ST:
449 case RT5682S_IL_CMD_1:
450 case RT5682S_4BTN_IL_CMD_1:
451 case RT5682S_AJD1_CTRL:
452 case RT5682S_VERSION_ID...RT5682S_DEVICE_ID:
453 case RT5682S_STO_NG2_CTRL_1:
454 case RT5682S_STO_NG2_CTRL_5...RT5682S_STO_NG2_CTRL_7:
455 case RT5682S_STO1_DAC_SIL_DET:
456 case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_4:
457 case RT5682S_HP_IMP_SENS_CTRL_13:
458 case RT5682S_HP_IMP_SENS_CTRL_14:
459 case RT5682S_HP_IMP_SENS_CTRL_43...RT5682S_HP_IMP_SENS_CTRL_46:
460 case RT5682S_HP_CALIB_CTRL_1:
461 case RT5682S_HP_CALIB_CTRL_10:
462 case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11:
463 case RT5682S_SAR_IL_CMD_2...RT5682S_SAR_IL_CMD_5:
464 case RT5682S_SAR_IL_CMD_10:
465 case RT5682S_SAR_IL_CMD_11:
466 case RT5682S_VERSION_ID_HIDE:
467 case RT5682S_VERSION_ID_CUS:
468 case RT5682S_I2C_TRANS_CTRL:
469 case RT5682S_DMIC_FLOAT_DET:
470 case RT5682S_HA_CMP_OP_1:
471 case RT5682S_NEW_CBJ_DET_CTL_10...RT5682S_NEW_CBJ_DET_CTL_16:
472 case RT5682S_CLK_SW_TEST_1:
473 case RT5682S_CLK_SW_TEST_2:
474 case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18:
475 case RT5682S_PILOT_DIG_CTL_1:
476 return true;
477 default:
478 return false;
479 }
480}
481
482static bool rt5682s_readable_register(struct device *dev, unsigned int reg)
483{
484 switch (reg) {
485 case RT5682S_RESET:
486 case RT5682S_VERSION_ID:
487 case RT5682S_VENDOR_ID:
488 case RT5682S_DEVICE_ID:
489 case RT5682S_HP_CTRL_1:
490 case RT5682S_HP_CTRL_2:
491 case RT5682S_HPL_GAIN:
492 case RT5682S_HPR_GAIN:
493 case RT5682S_I2C_CTRL:
494 case RT5682S_CBJ_BST_CTRL:
495 case RT5682S_CBJ_DET_CTRL:
496 case RT5682S_CBJ_CTRL_1...RT5682S_CBJ_CTRL_8:
497 case RT5682S_DAC1_DIG_VOL:
498 case RT5682S_STO1_ADC_DIG_VOL:
499 case RT5682S_STO1_ADC_BOOST:
500 case RT5682S_HP_IMP_GAIN_1:
501 case RT5682S_HP_IMP_GAIN_2:
502 case RT5682S_SIDETONE_CTRL:
503 case RT5682S_STO1_ADC_MIXER:
504 case RT5682S_AD_DA_MIXER:
505 case RT5682S_STO1_DAC_MIXER:
506 case RT5682S_A_DAC1_MUX:
507 case RT5682S_DIG_INF2_DATA:
508 case RT5682S_REC_MIXER:
509 case RT5682S_CAL_REC:
510 case RT5682S_HP_ANA_OST_CTRL_1...RT5682S_HP_ANA_OST_CTRL_3:
511 case RT5682S_PWR_DIG_1...RT5682S_PWR_MIXER:
512 case RT5682S_MB_CTRL:
513 case RT5682S_CLK_GATE_TCON_1...RT5682S_CLK_GATE_TCON_3:
514 case RT5682S_CLK_DET...RT5682S_LPF_AD_DMIC:
515 case RT5682S_I2S1_SDP:
516 case RT5682S_I2S2_SDP:
517 case RT5682S_ADDA_CLK_1:
518 case RT5682S_ADDA_CLK_2:
519 case RT5682S_I2S1_F_DIV_CTRL_1:
520 case RT5682S_I2S1_F_DIV_CTRL_2:
521 case RT5682S_TDM_CTRL:
522 case RT5682S_TDM_ADDA_CTRL_1:
523 case RT5682S_TDM_ADDA_CTRL_2:
524 case RT5682S_DATA_SEL_CTRL_1:
525 case RT5682S_TDM_TCON_CTRL_1:
526 case RT5682S_TDM_TCON_CTRL_2:
527 case RT5682S_GLB_CLK:
528 case RT5682S_PLL_TRACK_1...RT5682S_PLL_TRACK_6:
529 case RT5682S_PLL_TRACK_11:
530 case RT5682S_DEPOP_1:
531 case RT5682S_HP_CHARGE_PUMP_1:
532 case RT5682S_HP_CHARGE_PUMP_2:
533 case RT5682S_HP_CHARGE_PUMP_3:
534 case RT5682S_MICBIAS_1...RT5682S_MICBIAS_3:
535 case RT5682S_PLL_TRACK_12...RT5682S_PLL_CTRL_7:
536 case RT5682S_RC_CLK_CTRL:
537 case RT5682S_I2S2_M_CLK_CTRL_1:
538 case RT5682S_I2S2_F_DIV_CTRL_1:
539 case RT5682S_I2S2_F_DIV_CTRL_2:
540 case RT5682S_IRQ_CTRL_1...RT5682S_IRQ_CTRL_4:
541 case RT5682S_INT_ST_1:
542 case RT5682S_GPIO_CTRL_1:
543 case RT5682S_GPIO_CTRL_2:
544 case RT5682S_GPIO_ST:
545 case RT5682S_HP_AMP_DET_CTRL_1:
546 case RT5682S_MID_HP_AMP_DET:
547 case RT5682S_LOW_HP_AMP_DET:
548 case RT5682S_DELAY_BUF_CTRL:
549 case RT5682S_SV_ZCD_1:
550 case RT5682S_SV_ZCD_2:
551 case RT5682S_IL_CMD_1...RT5682S_IL_CMD_6:
552 case RT5682S_4BTN_IL_CMD_1...RT5682S_4BTN_IL_CMD_7:
553 case RT5682S_ADC_STO1_HP_CTRL_1:
554 case RT5682S_ADC_STO1_HP_CTRL_2:
555 case RT5682S_AJD1_CTRL:
556 case RT5682S_JD_CTRL_1:
557 case RT5682S_DUMMY_1...RT5682S_DUMMY_3:
558 case RT5682S_DAC_ADC_DIG_VOL1:
559 case RT5682S_BIAS_CUR_CTRL_2...RT5682S_BIAS_CUR_CTRL_10:
560 case RT5682S_VREF_REC_OP_FB_CAP_CTRL_1:
561 case RT5682S_VREF_REC_OP_FB_CAP_CTRL_2:
562 case RT5682S_CHARGE_PUMP_1:
563 case RT5682S_DIG_IN_CTRL_1:
564 case RT5682S_PAD_DRIVING_CTRL:
565 case RT5682S_CHOP_DAC_1:
566 case RT5682S_CHOP_DAC_2:
567 case RT5682S_CHOP_ADC:
568 case RT5682S_CALIB_ADC_CTRL:
569 case RT5682S_VOL_TEST:
570 case RT5682S_SPKVDD_DET_ST:
571 case RT5682S_TEST_MODE_CTRL_1...RT5682S_TEST_MODE_CTRL_4:
572 case RT5682S_PLL_INTERNAL_1...RT5682S_PLL_INTERNAL_4:
573 case RT5682S_STO_NG2_CTRL_1...RT5682S_STO_NG2_CTRL_10:
574 case RT5682S_STO1_DAC_SIL_DET:
575 case RT5682S_SIL_PSV_CTRL1:
576 case RT5682S_SIL_PSV_CTRL2:
577 case RT5682S_SIL_PSV_CTRL3:
578 case RT5682S_SIL_PSV_CTRL4:
579 case RT5682S_SIL_PSV_CTRL5:
580 case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_46:
581 case RT5682S_HP_LOGIC_CTRL_1...RT5682S_HP_LOGIC_CTRL_3:
582 case RT5682S_HP_CALIB_CTRL_1...RT5682S_HP_CALIB_CTRL_11:
583 case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11:
584 case RT5682S_SAR_IL_CMD_1...RT5682S_SAR_IL_CMD_14:
585 case RT5682S_DUMMY_4...RT5682S_DUMMY_6:
586 case RT5682S_VERSION_ID_HIDE:
587 case RT5682S_VERSION_ID_CUS:
588 case RT5682S_SCAN_CTL:
589 case RT5682S_HP_AMP_DET:
590 case RT5682S_BIAS_CUR_CTRL_11:
591 case RT5682S_BIAS_CUR_CTRL_12:
592 case RT5682S_BIAS_CUR_CTRL_13:
593 case RT5682S_BIAS_CUR_CTRL_14:
594 case RT5682S_BIAS_CUR_CTRL_15:
595 case RT5682S_BIAS_CUR_CTRL_16:
596 case RT5682S_BIAS_CUR_CTRL_17:
597 case RT5682S_BIAS_CUR_CTRL_18:
598 case RT5682S_I2C_TRANS_CTRL:
599 case RT5682S_DUMMY_7:
600 case RT5682S_DUMMY_8:
601 case RT5682S_DMIC_FLOAT_DET:
602 case RT5682S_HA_CMP_OP_1...RT5682S_HA_CMP_OP_13:
603 case RT5682S_HA_CMP_OP_14...RT5682S_HA_CMP_OP_25:
604 case RT5682S_NEW_CBJ_DET_CTL_1...RT5682S_NEW_CBJ_DET_CTL_16:
605 case RT5682S_DA_FILTER_1...RT5682S_DA_FILTER_5:
606 case RT5682S_CLK_SW_TEST_1:
607 case RT5682S_CLK_SW_TEST_2:
608 case RT5682S_CLK_SW_TEST_3...RT5682S_CLK_SW_TEST_14:
609 case RT5682S_EFUSE_MANU_WRITE_1...RT5682S_EFUSE_MANU_WRITE_6:
610 case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18:
611 case RT5682S_EFUSE_TIMING_CTL_1:
612 case RT5682S_EFUSE_TIMING_CTL_2:
613 case RT5682S_PILOT_DIG_CTL_1:
614 case RT5682S_PILOT_DIG_CTL_2:
615 case RT5682S_HP_AMP_DET_CTL_1...RT5682S_HP_AMP_DET_CTL_4:
616 return true;
617 default:
618 return false;
619 }
620}
621
622static void rt5682s_reset(struct rt5682s_priv *rt5682s)
623{
624 regmap_write(map: rt5682s->regmap, RT5682S_RESET, val: 0);
625}
626
627static int rt5682s_button_detect(struct snd_soc_component *component)
628{
629 int btn_type, val;
630
631 val = snd_soc_component_read(component, RT5682S_4BTN_IL_CMD_1);
632 btn_type = val & 0xfff0;
633 snd_soc_component_write(component, RT5682S_4BTN_IL_CMD_1, val);
634 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
635 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2,
636 RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY);
637
638 return btn_type;
639}
640
641enum {
642 SAR_PWR_OFF,
643 SAR_PWR_NORMAL,
644 SAR_PWR_SAVING,
645};
646
647static void rt5682s_sar_power_mode(struct snd_soc_component *component, int mode)
648{
649 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
650
651 mutex_lock(&rt5682s->sar_mutex);
652
653 switch (mode) {
654 case SAR_PWR_SAVING:
655 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
656 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN);
657 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
658 RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK |
659 RT5682S_VREF_POW_MASK, RT5682S_CTRL_MB1_FSM |
660 RT5682S_CTRL_MB2_FSM | RT5682S_VREF_POW_FSM);
661 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
662 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
663 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
664 RT5682S_SAR_BUTDET_POW_NORM | RT5682S_SAR_SEL_MB1_2_MANU);
665 usleep_range(min: 5000, max: 5500);
666 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
667 RT5682S_SAR_BUTDET_MASK, RT5682S_SAR_BUTDET_EN);
668 usleep_range(min: 5000, max: 5500);
669 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2,
670 RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY);
671 break;
672 case SAR_PWR_NORMAL:
673 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
674 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN);
675 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
676 RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
677 RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM);
678 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
679 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_SEL_MB1_2_AUTO);
680 usleep_range(min: 5000, max: 5500);
681 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
682 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK,
683 RT5682S_SAR_BUTDET_EN | RT5682S_SAR_BUTDET_POW_NORM);
684 break;
685 case SAR_PWR_OFF:
686 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
687 RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
688 RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM);
689 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
690 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
691 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
692 RT5682S_SAR_BUTDET_POW_NORM | RT5682S_SAR_SEL_MB1_2_MANU);
693 break;
694 default:
695 dev_err(component->dev, "Invalid SAR Power mode: %d\n", mode);
696 break;
697 }
698
699 mutex_unlock(lock: &rt5682s->sar_mutex);
700}
701
702static void rt5682s_enable_push_button_irq(struct snd_soc_component *component)
703{
704 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
705 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_BTN);
706 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
707 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
708 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_EN |
709 RT5682S_SAR_BUTDET_POW_NORM | RT5682S_SAR_SEL_MB1_2_AUTO);
710 snd_soc_component_write(component, RT5682S_IL_CMD_1, val: 0x0040);
711 snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2,
712 RT5682S_4BTN_IL_MASK | RT5682S_4BTN_IL_RST_MASK,
713 RT5682S_4BTN_IL_EN | RT5682S_4BTN_IL_NOR);
714 snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3,
715 RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_EN);
716}
717
718static void rt5682s_disable_push_button_irq(struct snd_soc_component *component)
719{
720 snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3,
721 RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_DIS);
722 snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2,
723 RT5682S_4BTN_IL_MASK, RT5682S_4BTN_IL_DIS);
724 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
725 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE);
726 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
727 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
728 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
729 RT5682S_SAR_BUTDET_POW_NORM | RT5682S_SAR_SEL_MB1_2_MANU);
730}
731
732/**
733 * rt5682s_headset_detect - Detect headset.
734 * @component: SoC audio component device.
735 * @jack_insert: Jack insert or not.
736 *
737 * Detect whether is headset or not when jack inserted.
738 *
739 * Returns detect status.
740 */
741static int rt5682s_headset_detect(struct snd_soc_component *component, int jack_insert)
742{
743 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
744 unsigned int val, count;
745 int jack_type = 0;
746
747 if (jack_insert) {
748 rt5682s_disable_push_button_irq(component);
749 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
750 RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB,
751 RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
752 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
753 RT5682S_PWR_FV1 | RT5682S_PWR_FV2, val: 0);
754 usleep_range(min: 15000, max: 20000);
755 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
756 RT5682S_PWR_FV1 | RT5682S_PWR_FV2,
757 RT5682S_PWR_FV1 | RT5682S_PWR_FV2);
758 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
759 RT5682S_PWR_CBJ, RT5682S_PWR_CBJ);
760 snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, val: 0x0365);
761 snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2,
762 RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK,
763 RT5682S_OSW_L_DIS | RT5682S_OSW_R_DIS);
764 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
765 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE);
766 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
767 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN);
768 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
769 RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW);
770 usleep_range(min: 45000, max: 50000);
771 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
772 RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_HIGH);
773
774 count = 0;
775 do {
776 usleep_range(min: 10000, max: 15000);
777 val = snd_soc_component_read(component, RT5682S_CBJ_CTRL_2)
778 & RT5682S_JACK_TYPE_MASK;
779 count++;
780 } while (val == 0 && count < 50);
781
782 dev_dbg(component->dev, "%s, val=%d, count=%d\n", __func__, val, count);
783
784 switch (val) {
785 case 0x1:
786 case 0x2:
787 jack_type = SND_JACK_HEADSET;
788 snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, val: 0x024c);
789 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
790 RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_DIS);
791 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
792 RT5682S_SAR_SEL_MB1_2_MASK, val: val << RT5682S_SAR_SEL_MB1_2_SFT);
793 rt5682s_enable_push_button_irq(component);
794 rt5682s_sar_power_mode(component, mode: SAR_PWR_SAVING);
795 break;
796 default:
797 jack_type = SND_JACK_HEADPHONE;
798 break;
799 }
800 snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2,
801 RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK,
802 RT5682S_OSW_L_EN | RT5682S_OSW_R_EN);
803 usleep_range(min: 35000, max: 40000);
804 } else {
805 rt5682s_sar_power_mode(component, mode: SAR_PWR_OFF);
806 rt5682s_disable_push_button_irq(component);
807 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
808 RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW);
809
810 if (!rt5682s->wclk_enabled) {
811 snd_soc_component_update_bits(component,
812 RT5682S_PWR_ANLG_1, RT5682S_PWR_VREF2 | RT5682S_PWR_MB, val: 0);
813 }
814
815 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
816 RT5682S_PWR_CBJ, val: 0);
817 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
818 RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_DIS);
819 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
820 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS);
821 jack_type = 0;
822 }
823
824 dev_dbg(component->dev, "jack_type = %d\n", jack_type);
825
826 return jack_type;
827}
828
829static void rt5682s_jack_detect_handler(struct work_struct *work)
830{
831 struct rt5682s_priv *rt5682s =
832 container_of(work, struct rt5682s_priv, jack_detect_work.work);
833 struct snd_soc_dapm_context *dapm;
834 int val, btn_type;
835
836 if (!rt5682s->component ||
837 !snd_soc_card_is_instantiated(card: rt5682s->component->card)) {
838 /* card not yet ready, try later */
839 mod_delayed_work(wq: system_power_efficient_wq,
840 dwork: &rt5682s->jack_detect_work, delay: msecs_to_jiffies(m: 15));
841 return;
842 }
843
844 dapm = snd_soc_component_to_dapm(component: rt5682s->component);
845
846 snd_soc_dapm_mutex_lock(dapm);
847 mutex_lock(&rt5682s->calibrate_mutex);
848 mutex_lock(&rt5682s->wclk_mutex);
849
850 val = snd_soc_component_read(component: rt5682s->component, RT5682S_AJD1_CTRL)
851 & RT5682S_JDH_RS_MASK;
852 if (!val) {
853 /* jack in */
854 if (rt5682s->jack_type == 0) {
855 /* jack was out, report jack type */
856 rt5682s->jack_type = rt5682s_headset_detect(component: rt5682s->component, jack_insert: 1);
857 rt5682s->irq_work_delay_time = 0;
858 } else if ((rt5682s->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
859 /* jack is already in, report button event */
860 rt5682s->jack_type = SND_JACK_HEADSET;
861 btn_type = rt5682s_button_detect(component: rt5682s->component);
862 /**
863 * rt5682s can report three kinds of button behavior,
864 * one click, double click and hold. However,
865 * currently we will report button pressed/released
866 * event. So all the three button behaviors are
867 * treated as button pressed.
868 */
869 switch (btn_type) {
870 case 0x8000:
871 case 0x4000:
872 case 0x2000:
873 rt5682s->jack_type |= SND_JACK_BTN_0;
874 break;
875 case 0x1000:
876 case 0x0800:
877 case 0x0400:
878 rt5682s->jack_type |= SND_JACK_BTN_1;
879 break;
880 case 0x0200:
881 case 0x0100:
882 case 0x0080:
883 rt5682s->jack_type |= SND_JACK_BTN_2;
884 break;
885 case 0x0040:
886 case 0x0020:
887 case 0x0010:
888 rt5682s->jack_type |= SND_JACK_BTN_3;
889 break;
890 case 0x0000: /* unpressed */
891 break;
892 default:
893 dev_err(rt5682s->component->dev,
894 "Unexpected button code 0x%04x\n", btn_type);
895 break;
896 }
897 }
898 } else {
899 /* jack out */
900 rt5682s->jack_type = rt5682s_headset_detect(component: rt5682s->component, jack_insert: 0);
901 rt5682s->irq_work_delay_time = 50;
902 }
903
904 mutex_unlock(lock: &rt5682s->wclk_mutex);
905 mutex_unlock(lock: &rt5682s->calibrate_mutex);
906 snd_soc_dapm_mutex_unlock(dapm);
907
908 snd_soc_jack_report(jack: rt5682s->hs_jack, status: rt5682s->jack_type,
909 mask: SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 |
910 SND_JACK_BTN_2 | SND_JACK_BTN_3);
911
912 if (rt5682s->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
913 SND_JACK_BTN_2 | SND_JACK_BTN_3))
914 schedule_delayed_work(dwork: &rt5682s->jd_check_work, delay: 0);
915 else
916 cancel_delayed_work_sync(dwork: &rt5682s->jd_check_work);
917}
918
919static void rt5682s_jd_check_handler(struct work_struct *work)
920{
921 struct rt5682s_priv *rt5682s =
922 container_of(work, struct rt5682s_priv, jd_check_work.work);
923
924 if (snd_soc_component_read(component: rt5682s->component, RT5682S_AJD1_CTRL) & RT5682S_JDH_RS_MASK) {
925 /* jack out */
926 schedule_delayed_work(dwork: &rt5682s->jack_detect_work, delay: 0);
927 } else {
928 schedule_delayed_work(dwork: &rt5682s->jd_check_work, delay: 500);
929 }
930}
931
932static irqreturn_t rt5682s_irq(int irq, void *data)
933{
934 struct rt5682s_priv *rt5682s = data;
935
936 mod_delayed_work(wq: system_power_efficient_wq, dwork: &rt5682s->jack_detect_work,
937 delay: msecs_to_jiffies(m: rt5682s->irq_work_delay_time));
938
939 return IRQ_HANDLED;
940}
941
942static int rt5682s_set_jack_detect(struct snd_soc_component *component,
943 struct snd_soc_jack *hs_jack, void *data)
944{
945 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
946 int btndet_delay = 16;
947
948 rt5682s->hs_jack = hs_jack;
949
950 if (!hs_jack) {
951 regmap_update_bits(map: rt5682s->regmap, RT5682S_IRQ_CTRL_2,
952 RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS);
953 regmap_update_bits(map: rt5682s->regmap, RT5682S_RC_CLK_CTRL,
954 RT5682S_POW_JDH, val: 0);
955 cancel_delayed_work_sync(dwork: &rt5682s->jack_detect_work);
956
957 return 0;
958 }
959
960 switch (rt5682s->pdata.jd_src) {
961 case RT5682S_JD1:
962 regmap_update_bits(map: rt5682s->regmap, RT5682S_CBJ_CTRL_5,
963 RT5682S_JD_FAST_OFF_SRC_MASK, RT5682S_JD_FAST_OFF_SRC_JDH);
964 regmap_update_bits(map: rt5682s->regmap, RT5682S_CBJ_CTRL_2,
965 RT5682S_EXT_JD_SRC, RT5682S_EXT_JD_SRC_MANUAL);
966 regmap_update_bits(map: rt5682s->regmap, RT5682S_CBJ_CTRL_1,
967 RT5682S_EMB_JD_MASK | RT5682S_DET_TYPE |
968 RT5682S_POL_FAST_OFF_MASK | RT5682S_MIC_CAP_MASK,
969 RT5682S_EMB_JD_EN | RT5682S_DET_TYPE |
970 RT5682S_POL_FAST_OFF_LOW | RT5682S_MIC_CAP_HS);
971 regmap_update_bits(map: rt5682s->regmap, RT5682S_SAR_IL_CMD_1,
972 RT5682S_SAR_POW_MASK, RT5682S_SAR_POW_EN);
973 regmap_update_bits(map: rt5682s->regmap, RT5682S_GPIO_CTRL_1,
974 RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_IRQ);
975 regmap_update_bits(map: rt5682s->regmap, RT5682S_PWR_ANLG_3,
976 RT5682S_PWR_BGLDO, RT5682S_PWR_BGLDO);
977 regmap_update_bits(map: rt5682s->regmap, RT5682S_PWR_ANLG_2,
978 RT5682S_PWR_JD_MASK, RT5682S_PWR_JD_ENABLE);
979 regmap_update_bits(map: rt5682s->regmap, RT5682S_RC_CLK_CTRL,
980 RT5682S_POW_IRQ | RT5682S_POW_JDH, RT5682S_POW_IRQ | RT5682S_POW_JDH);
981 regmap_update_bits(map: rt5682s->regmap, RT5682S_IRQ_CTRL_2,
982 RT5682S_JD1_EN_MASK | RT5682S_JD1_POL_MASK,
983 RT5682S_JD1_EN | RT5682S_JD1_POL_NOR);
984 regmap_update_bits(map: rt5682s->regmap, RT5682S_4BTN_IL_CMD_4,
985 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
986 val: (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
987 regmap_update_bits(map: rt5682s->regmap, RT5682S_4BTN_IL_CMD_5,
988 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
989 val: (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
990 regmap_update_bits(map: rt5682s->regmap, RT5682S_4BTN_IL_CMD_6,
991 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
992 val: (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
993 regmap_update_bits(map: rt5682s->regmap, RT5682S_4BTN_IL_CMD_7,
994 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
995 val: (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
996
997 mod_delayed_work(wq: system_power_efficient_wq,
998 dwork: &rt5682s->jack_detect_work, delay: msecs_to_jiffies(m: 250));
999 break;
1000
1001 case RT5682S_JD_NULL:
1002 regmap_update_bits(map: rt5682s->regmap, RT5682S_IRQ_CTRL_2,
1003 RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS);
1004 regmap_update_bits(map: rt5682s->regmap, RT5682S_RC_CLK_CTRL,
1005 RT5682S_POW_JDH, val: 0);
1006 break;
1007
1008 default:
1009 dev_warn(component->dev, "Wrong JD source\n");
1010 break;
1011 }
1012
1013 return 0;
1014}
1015
1016static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9562, 75, 0);
1017static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1018static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
1019static const DECLARE_TLV_DB_SCALE(cbj_bst_tlv, -1200, 150, 0);
1020
1021static const struct snd_kcontrol_new rt5682s_snd_controls[] = {
1022 /* DAC Digital Volume */
1023 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682S_DAC1_DIG_VOL,
1024 RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 127, 0, dac_vol_tlv),
1025
1026 /* CBJ Boost Volume */
1027 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682S_REC_MIXER,
1028 RT5682S_BST_CBJ_SFT, 35, 0, cbj_bst_tlv),
1029
1030 /* ADC Digital Volume Control */
1031 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682S_STO1_ADC_DIG_VOL,
1032 RT5682S_L_MUTE_SFT, RT5682S_R_MUTE_SFT, 1, 1),
1033 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682S_STO1_ADC_DIG_VOL,
1034 RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1035
1036 /* ADC Boost Volume Control */
1037 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682S_STO1_ADC_BOOST,
1038 RT5682S_STO1_ADC_L_BST_SFT, RT5682S_STO1_ADC_R_BST_SFT, 3, 0, adc_bst_tlv),
1039};
1040
1041/**
1042 * rt5682s_sel_asrc_clk_src - select ASRC clock source for a set of filters
1043 * @component: SoC audio component device.
1044 * @filter_mask: mask of filters.
1045 * @clk_src: clock source
1046 *
1047 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682S can
1048 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1049 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1050 * ASRC function will track i2s clock and generate a corresponding system clock
1051 * for codec. This function provides an API to select the clock source for a
1052 * set of filters specified by the mask. And the component driver will turn on
1053 * ASRC for these filters if ASRC is selected as their clock source.
1054 */
1055int rt5682s_sel_asrc_clk_src(struct snd_soc_component *component,
1056 unsigned int filter_mask, unsigned int clk_src)
1057{
1058 switch (clk_src) {
1059 case RT5682S_CLK_SEL_SYS:
1060 case RT5682S_CLK_SEL_I2S1_ASRC:
1061 case RT5682S_CLK_SEL_I2S2_ASRC:
1062 break;
1063
1064 default:
1065 return -EINVAL;
1066 }
1067
1068 if (filter_mask & RT5682S_DA_STEREO1_FILTER) {
1069 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_2,
1070 RT5682S_FILTER_CLK_SEL_MASK, val: clk_src << RT5682S_FILTER_CLK_SEL_SFT);
1071 }
1072
1073 if (filter_mask & RT5682S_AD_STEREO1_FILTER) {
1074 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_3,
1075 RT5682S_FILTER_CLK_SEL_MASK, val: clk_src << RT5682S_FILTER_CLK_SEL_SFT);
1076 }
1077
1078 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_11,
1079 RT5682S_ASRCIN_AUTO_CLKOUT_MASK, RT5682S_ASRCIN_AUTO_CLKOUT_EN);
1080
1081 return 0;
1082}
1083EXPORT_SYMBOL_GPL(rt5682s_sel_asrc_clk_src);
1084
1085static int rt5682s_div_sel(struct rt5682s_priv *rt5682s,
1086 int target, const int div[], int size)
1087{
1088 int i;
1089
1090 if (rt5682s->sysclk < target) {
1091 dev_err(rt5682s->component->dev,
1092 "sysclk rate %d is too low\n", rt5682s->sysclk);
1093 return 0;
1094 }
1095
1096 for (i = 0; i < size - 1; i++) {
1097 dev_dbg(rt5682s->component->dev, "div[%d]=%d\n", i, div[i]);
1098 if (target * div[i] == rt5682s->sysclk)
1099 return i;
1100 if (target * div[i + 1] > rt5682s->sysclk) {
1101 dev_dbg(rt5682s->component->dev,
1102 "can't find div for sysclk %d\n", rt5682s->sysclk);
1103 return i;
1104 }
1105 }
1106
1107 if (target * div[i] < rt5682s->sysclk)
1108 dev_err(rt5682s->component->dev,
1109 "sysclk rate %d is too high\n", rt5682s->sysclk);
1110
1111 return size - 1;
1112}
1113
1114static int get_clk_info(int sclk, int rate)
1115{
1116 int i;
1117 static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1118
1119 if (sclk <= 0 || rate <= 0)
1120 return -EINVAL;
1121
1122 rate = rate << 8;
1123 for (i = 0; i < ARRAY_SIZE(pd); i++)
1124 if (sclk == rate * pd[i])
1125 return i;
1126
1127 return -EINVAL;
1128}
1129
1130/**
1131 * set_dmic_clk - Set parameter of dmic.
1132 *
1133 * @w: DAPM widget.
1134 * @kcontrol: The kcontrol of this widget.
1135 * @event: Event id.
1136 *
1137 * Choose dmic clock between 1MHz and 3MHz.
1138 * It is better for clock to approximate 3MHz.
1139 */
1140static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1141 struct snd_kcontrol *kcontrol, int event)
1142{
1143 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1144 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
1145 int idx, dmic_clk_rate = 3072000;
1146 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1147
1148 if (rt5682s->pdata.dmic_clk_rate)
1149 dmic_clk_rate = rt5682s->pdata.dmic_clk_rate;
1150
1151 idx = rt5682s_div_sel(rt5682s, target: dmic_clk_rate, div, ARRAY_SIZE(div));
1152
1153 snd_soc_component_update_bits(component, RT5682S_DMIC_CTRL_1,
1154 RT5682S_DMIC_CLK_MASK, val: idx << RT5682S_DMIC_CLK_SFT);
1155
1156 return 0;
1157}
1158
1159
1160static int rt5682s_set_pllb_power(struct rt5682s_priv *rt5682s, int on)
1161{
1162 struct snd_soc_component *component = rt5682s->component;
1163
1164 if (on) {
1165 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
1166 RT5682S_PWR_LDO_PLLB | RT5682S_PWR_BIAS_PLLB | RT5682S_PWR_PLLB,
1167 RT5682S_PWR_LDO_PLLB | RT5682S_PWR_BIAS_PLLB | RT5682S_PWR_PLLB);
1168 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
1169 RT5682S_RSTB_PLLB, RT5682S_RSTB_PLLB);
1170 } else {
1171 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
1172 RT5682S_PWR_LDO_PLLB | RT5682S_PWR_BIAS_PLLB |
1173 RT5682S_RSTB_PLLB | RT5682S_PWR_PLLB, val: 0);
1174 }
1175
1176 return 0;
1177}
1178
1179static int set_pllb_event(struct snd_soc_dapm_widget *w,
1180 struct snd_kcontrol *kcontrol, int event)
1181{
1182 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1183 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
1184 int on = 0;
1185
1186 if (rt5682s->wclk_enabled)
1187 return 0;
1188
1189 if (SND_SOC_DAPM_EVENT_ON(event))
1190 on = 1;
1191
1192 rt5682s_set_pllb_power(rt5682s, on);
1193
1194 return 0;
1195}
1196
1197static void rt5682s_set_filter_clk(struct rt5682s_priv *rt5682s, int reg, int ref)
1198{
1199 struct snd_soc_component *component = rt5682s->component;
1200 int idx;
1201 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1202 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1203
1204 idx = rt5682s_div_sel(rt5682s, target: ref, div: div_f, ARRAY_SIZE(div_f));
1205
1206 snd_soc_component_update_bits(component, reg,
1207 RT5682S_FILTER_CLK_DIV_MASK, val: idx << RT5682S_FILTER_CLK_DIV_SFT);
1208
1209 /* select over sample rate */
1210 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1211 if (rt5682s->sysclk <= 12288000 * div_o[idx])
1212 break;
1213 }
1214
1215 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1,
1216 RT5682S_ADC_OSR_MASK | RT5682S_DAC_OSR_MASK,
1217 val: (idx << RT5682S_ADC_OSR_SFT) | (idx << RT5682S_DAC_OSR_SFT));
1218}
1219
1220static int set_filter_clk(struct snd_soc_dapm_widget *w,
1221 struct snd_kcontrol *kcontrol, int event)
1222{
1223 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1224 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
1225 int ref, reg, val;
1226
1227 val = snd_soc_component_read(component, RT5682S_GPIO_CTRL_1)
1228 & RT5682S_GP4_PIN_MASK;
1229
1230 if (w->shift == RT5682S_PWR_ADC_S1F_BIT && val == RT5682S_GP4_PIN_ADCDAT2)
1231 ref = 256 * rt5682s->lrck[RT5682S_AIF2];
1232 else
1233 ref = 256 * rt5682s->lrck[RT5682S_AIF1];
1234
1235 if (w->shift == RT5682S_PWR_ADC_S1F_BIT)
1236 reg = RT5682S_PLL_TRACK_3;
1237 else
1238 reg = RT5682S_PLL_TRACK_2;
1239
1240 rt5682s_set_filter_clk(rt5682s, reg, ref);
1241
1242 return 0;
1243}
1244
1245static int set_dmic_power(struct snd_soc_dapm_widget *w,
1246 struct snd_kcontrol *kcontrol, int event)
1247{
1248 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1249 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
1250 unsigned int delay = 50, val;
1251
1252 if (rt5682s->pdata.dmic_delay)
1253 delay = rt5682s->pdata.dmic_delay;
1254
1255 switch (event) {
1256 case SND_SOC_DAPM_POST_PMU:
1257 val = (snd_soc_component_read(component, RT5682S_GLB_CLK)
1258 & RT5682S_SCLK_SRC_MASK) >> RT5682S_SCLK_SRC_SFT;
1259 if (val == RT5682S_CLK_SRC_PLL1 || val == RT5682S_CLK_SRC_PLL2)
1260 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
1261 RT5682S_PWR_VREF2 | RT5682S_PWR_MB,
1262 RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
1263
1264 /*Add delay to avoid pop noise*/
1265 msleep(msecs: delay);
1266 break;
1267
1268 case SND_SOC_DAPM_POST_PMD:
1269 if (!rt5682s->jack_type && !rt5682s->wclk_enabled) {
1270 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
1271 RT5682S_PWR_VREF2 | RT5682S_PWR_MB, val: 0);
1272 }
1273 break;
1274 }
1275
1276 return 0;
1277}
1278
1279static void rt5682s_set_i2s(struct rt5682s_priv *rt5682s, int id, int on)
1280{
1281 struct snd_soc_component *component = rt5682s->component;
1282 int pre_div;
1283 unsigned int p_reg, p_mask, p_sft;
1284 unsigned int c_reg, c_mask, c_sft;
1285
1286 if (id == RT5682S_AIF1) {
1287 c_reg = RT5682S_ADDA_CLK_1;
1288 c_mask = RT5682S_I2S_M_D_MASK;
1289 c_sft = RT5682S_I2S_M_D_SFT;
1290 p_reg = RT5682S_PWR_DIG_1;
1291 p_mask = RT5682S_PWR_I2S1;
1292 p_sft = RT5682S_PWR_I2S1_BIT;
1293 } else {
1294 c_reg = RT5682S_I2S2_M_CLK_CTRL_1;
1295 c_mask = RT5682S_I2S2_M_D_MASK;
1296 c_sft = RT5682S_I2S2_M_D_SFT;
1297 p_reg = RT5682S_PWR_DIG_1;
1298 p_mask = RT5682S_PWR_I2S2;
1299 p_sft = RT5682S_PWR_I2S2_BIT;
1300 }
1301
1302 if (on && rt5682s->master[id]) {
1303 pre_div = get_clk_info(sclk: rt5682s->sysclk, rate: rt5682s->lrck[id]);
1304 if (pre_div < 0) {
1305 dev_err(component->dev, "get pre_div failed\n");
1306 return;
1307 }
1308
1309 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d master\n",
1310 rt5682s->lrck[id], pre_div, id);
1311 snd_soc_component_update_bits(component, reg: c_reg, mask: c_mask, val: pre_div << c_sft);
1312 }
1313
1314 snd_soc_component_update_bits(component, reg: p_reg, mask: p_mask, val: on << p_sft);
1315}
1316
1317static int set_i2s_event(struct snd_soc_dapm_widget *w,
1318 struct snd_kcontrol *kcontrol, int event)
1319{
1320 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1321 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
1322 int on = 0;
1323
1324 if (SND_SOC_DAPM_EVENT_ON(event))
1325 on = 1;
1326
1327 if (!snd_soc_dapm_widget_name_cmp(widget: w, s: "I2S1") && !rt5682s->wclk_enabled)
1328 rt5682s_set_i2s(rt5682s, id: RT5682S_AIF1, on);
1329 else if (!snd_soc_dapm_widget_name_cmp(widget: w, s: "I2S2"))
1330 rt5682s_set_i2s(rt5682s, id: RT5682S_AIF2, on);
1331
1332 return 0;
1333}
1334
1335static int is_sys_clk_from_plla(struct snd_soc_dapm_widget *w,
1336 struct snd_soc_dapm_widget *sink)
1337{
1338 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1339 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
1340
1341 if ((rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL1) ||
1342 (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2 && rt5682s->pll_comb == USE_PLLAB))
1343 return 1;
1344
1345 return 0;
1346}
1347
1348static int is_sys_clk_from_pllb(struct snd_soc_dapm_widget *w,
1349 struct snd_soc_dapm_widget *sink)
1350{
1351 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1352 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
1353
1354 if (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2)
1355 return 1;
1356
1357 return 0;
1358}
1359
1360static int is_using_asrc(struct snd_soc_dapm_widget *w,
1361 struct snd_soc_dapm_widget *sink)
1362{
1363 unsigned int reg, sft, val;
1364 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1365
1366 switch (w->shift) {
1367 case RT5682S_ADC_STO1_ASRC_SFT:
1368 reg = RT5682S_PLL_TRACK_3;
1369 sft = RT5682S_FILTER_CLK_SEL_SFT;
1370 break;
1371 case RT5682S_DAC_STO1_ASRC_SFT:
1372 reg = RT5682S_PLL_TRACK_2;
1373 sft = RT5682S_FILTER_CLK_SEL_SFT;
1374 break;
1375 default:
1376 return 0;
1377 }
1378
1379 val = (snd_soc_component_read(component, reg) >> sft) & 0xf;
1380 switch (val) {
1381 case RT5682S_CLK_SEL_I2S1_ASRC:
1382 case RT5682S_CLK_SEL_I2S2_ASRC:
1383 return 1;
1384 default:
1385 return 0;
1386 }
1387}
1388
1389static int rt5682s_hp_amp_event(struct snd_soc_dapm_widget *w,
1390 struct snd_kcontrol *kcontrol, int event)
1391{
1392 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1393
1394 switch (event) {
1395 case SND_SOC_DAPM_POST_PMU:
1396 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1397 RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN,
1398 RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN);
1399 usleep_range(min: 15000, max: 20000);
1400 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1401 RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1402 RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN,
1403 RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1404 RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN);
1405 snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_11, val: 0x6666);
1406 snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_12, val: 0xa82a);
1407
1408 snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2,
1409 RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK |
1410 RT5682S_HPO_SEL_IP_EN_SW, RT5682S_HPO_L_PATH_EN |
1411 RT5682S_HPO_R_PATH_EN | RT5682S_HPO_IP_EN_GATING);
1412 usleep_range(min: 5000, max: 10000);
1413 snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1,
1414 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_L | RT5682S_CP_SW_SIZE_S);
1415 break;
1416
1417 case SND_SOC_DAPM_POST_PMD:
1418 snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2,
1419 RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK |
1420 RT5682S_HPO_SEL_IP_EN_SW, val: 0);
1421 snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1,
1422 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M);
1423 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1424 RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1425 RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN, val: 0);
1426 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1427 RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN, val: 0);
1428 break;
1429 }
1430
1431 return 0;
1432}
1433
1434static int rt5682s_stereo1_adc_mixl_event(struct snd_soc_dapm_widget *w,
1435 struct snd_kcontrol *kcontrol, int event)
1436{
1437 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1438 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
1439 unsigned int delay = 0;
1440
1441 if (rt5682s->pdata.amic_delay)
1442 delay = rt5682s->pdata.amic_delay;
1443
1444 switch (event) {
1445 case SND_SOC_DAPM_POST_PMU:
1446 msleep(msecs: delay);
1447 snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL,
1448 RT5682S_L_MUTE, val: 0);
1449 break;
1450 case SND_SOC_DAPM_PRE_PMD:
1451 snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL,
1452 RT5682S_L_MUTE, RT5682S_L_MUTE);
1453 break;
1454 }
1455
1456 return 0;
1457}
1458
1459static int sar_power_event(struct snd_soc_dapm_widget *w,
1460 struct snd_kcontrol *kcontrol, int event)
1461{
1462 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1463 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
1464
1465 if ((rt5682s->jack_type & SND_JACK_HEADSET) != SND_JACK_HEADSET)
1466 return 0;
1467
1468 switch (event) {
1469 case SND_SOC_DAPM_PRE_PMU:
1470 rt5682s_sar_power_mode(component, mode: SAR_PWR_NORMAL);
1471 break;
1472 case SND_SOC_DAPM_POST_PMD:
1473 rt5682s_sar_power_mode(component, mode: SAR_PWR_SAVING);
1474 break;
1475 }
1476
1477 return 0;
1478}
1479
1480/* Interface data select */
1481static const char * const rt5682s_data_select[] = {
1482 "L/R", "R/L", "L/L", "R/R"
1483};
1484
1485static SOC_ENUM_SINGLE_DECL(rt5682s_if2_adc_enum, RT5682S_DIG_INF2_DATA,
1486 RT5682S_IF2_ADC_SEL_SFT, rt5682s_data_select);
1487
1488static SOC_ENUM_SINGLE_DECL(rt5682s_if1_01_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1489 RT5682S_IF1_ADC1_SEL_SFT, rt5682s_data_select);
1490
1491static SOC_ENUM_SINGLE_DECL(rt5682s_if1_23_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1492 RT5682S_IF1_ADC2_SEL_SFT, rt5682s_data_select);
1493
1494static SOC_ENUM_SINGLE_DECL(rt5682s_if1_45_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1495 RT5682S_IF1_ADC3_SEL_SFT, rt5682s_data_select);
1496
1497static SOC_ENUM_SINGLE_DECL(rt5682s_if1_67_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1498 RT5682S_IF1_ADC4_SEL_SFT, rt5682s_data_select);
1499
1500static const struct snd_kcontrol_new rt5682s_if2_adc_swap_mux =
1501 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682s_if2_adc_enum);
1502
1503static const struct snd_kcontrol_new rt5682s_if1_01_adc_swap_mux =
1504 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682s_if1_01_adc_enum);
1505
1506static const struct snd_kcontrol_new rt5682s_if1_23_adc_swap_mux =
1507 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682s_if1_23_adc_enum);
1508
1509static const struct snd_kcontrol_new rt5682s_if1_45_adc_swap_mux =
1510 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682s_if1_45_adc_enum);
1511
1512static const struct snd_kcontrol_new rt5682s_if1_67_adc_swap_mux =
1513 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682s_if1_67_adc_enum);
1514
1515/* Digital Mixer */
1516static const struct snd_kcontrol_new rt5682s_sto1_adc_l_mix[] = {
1517 SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER,
1518 RT5682S_M_STO1_ADC_L1_SFT, 1, 1),
1519 SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER,
1520 RT5682S_M_STO1_ADC_L2_SFT, 1, 1),
1521};
1522
1523static const struct snd_kcontrol_new rt5682s_sto1_adc_r_mix[] = {
1524 SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER,
1525 RT5682S_M_STO1_ADC_R1_SFT, 1, 1),
1526 SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER,
1527 RT5682S_M_STO1_ADC_R2_SFT, 1, 1),
1528};
1529
1530static const struct snd_kcontrol_new rt5682s_dac_l_mix[] = {
1531 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER,
1532 RT5682S_M_ADCMIX_L_SFT, 1, 1),
1533 SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER,
1534 RT5682S_M_DAC1_L_SFT, 1, 1),
1535};
1536
1537static const struct snd_kcontrol_new rt5682s_dac_r_mix[] = {
1538 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER,
1539 RT5682S_M_ADCMIX_R_SFT, 1, 1),
1540 SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER,
1541 RT5682S_M_DAC1_R_SFT, 1, 1),
1542};
1543
1544static const struct snd_kcontrol_new rt5682s_sto1_dac_l_mix[] = {
1545 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER,
1546 RT5682S_M_DAC_L1_STO_L_SFT, 1, 1),
1547 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER,
1548 RT5682S_M_DAC_R1_STO_L_SFT, 1, 1),
1549};
1550
1551static const struct snd_kcontrol_new rt5682s_sto1_dac_r_mix[] = {
1552 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER,
1553 RT5682S_M_DAC_L1_STO_R_SFT, 1, 1),
1554 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER,
1555 RT5682S_M_DAC_R1_STO_R_SFT, 1, 1),
1556};
1557
1558/* Analog Input Mixer */
1559static const struct snd_kcontrol_new rt5682s_rec1_l_mix[] = {
1560 SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER,
1561 RT5682S_M_CBJ_RM1_L_SFT, 1, 1),
1562};
1563
1564static const struct snd_kcontrol_new rt5682s_rec1_r_mix[] = {
1565 SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER,
1566 RT5682S_M_CBJ_RM1_R_SFT, 1, 1),
1567};
1568
1569/* STO1 ADC1 Source */
1570/* MX-26 [13] [5] */
1571static const char * const rt5682s_sto1_adc1_src[] = {
1572 "DAC MIX", "ADC"
1573};
1574
1575static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1l_enum, RT5682S_STO1_ADC_MIXER,
1576 RT5682S_STO1_ADC1L_SRC_SFT, rt5682s_sto1_adc1_src);
1577
1578static const struct snd_kcontrol_new rt5682s_sto1_adc1l_mux =
1579 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1l_enum);
1580
1581static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1r_enum, RT5682S_STO1_ADC_MIXER,
1582 RT5682S_STO1_ADC1R_SRC_SFT, rt5682s_sto1_adc1_src);
1583
1584static const struct snd_kcontrol_new rt5682s_sto1_adc1r_mux =
1585 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1r_enum);
1586
1587/* STO1 ADC Source */
1588/* MX-26 [11:10] [3:2] */
1589static const char * const rt5682s_sto1_adc_src[] = {
1590 "ADC1 L", "ADC1 R"
1591};
1592
1593static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcl_enum, RT5682S_STO1_ADC_MIXER,
1594 RT5682S_STO1_ADCL_SRC_SFT, rt5682s_sto1_adc_src);
1595
1596static const struct snd_kcontrol_new rt5682s_sto1_adcl_mux =
1597 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682s_sto1_adcl_enum);
1598
1599static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcr_enum, RT5682S_STO1_ADC_MIXER,
1600 RT5682S_STO1_ADCR_SRC_SFT, rt5682s_sto1_adc_src);
1601
1602static const struct snd_kcontrol_new rt5682s_sto1_adcr_mux =
1603 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682s_sto1_adcr_enum);
1604
1605/* STO1 ADC2 Source */
1606/* MX-26 [12] [4] */
1607static const char * const rt5682s_sto1_adc2_src[] = {
1608 "DAC MIX", "DMIC"
1609};
1610
1611static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2l_enum, RT5682S_STO1_ADC_MIXER,
1612 RT5682S_STO1_ADC2L_SRC_SFT, rt5682s_sto1_adc2_src);
1613
1614static const struct snd_kcontrol_new rt5682s_sto1_adc2l_mux =
1615 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682s_sto1_adc2l_enum);
1616
1617static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2r_enum, RT5682S_STO1_ADC_MIXER,
1618 RT5682S_STO1_ADC2R_SRC_SFT, rt5682s_sto1_adc2_src);
1619
1620static const struct snd_kcontrol_new rt5682s_sto1_adc2r_mux =
1621 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682s_sto1_adc2r_enum);
1622
1623/* MX-79 [6:4] I2S1 ADC data location */
1624static const unsigned int rt5682s_if1_adc_slot_values[] = {
1625 0, 2, 4, 6,
1626};
1627
1628static const char * const rt5682s_if1_adc_slot_src[] = {
1629 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1630};
1631
1632static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_if1_adc_slot_enum,
1633 RT5682S_TDM_CTRL, RT5682S_TDM_ADC_LCA_SFT, RT5682S_TDM_ADC_LCA_MASK,
1634 rt5682s_if1_adc_slot_src, rt5682s_if1_adc_slot_values);
1635
1636static const struct snd_kcontrol_new rt5682s_if1_adc_slot_mux =
1637 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682s_if1_adc_slot_enum);
1638
1639/* Analog DAC L1 Source, Analog DAC R1 Source*/
1640/* MX-2B [4], MX-2B [0]*/
1641static const char * const rt5682s_alg_dac1_src[] = {
1642 "Stereo1 DAC Mixer", "DAC1"
1643};
1644
1645static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_l1_enum, RT5682S_A_DAC1_MUX,
1646 RT5682S_A_DACL1_SFT, rt5682s_alg_dac1_src);
1647
1648static const struct snd_kcontrol_new rt5682s_alg_dac_l1_mux =
1649 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682s_alg_dac_l1_enum);
1650
1651static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_r1_enum, RT5682S_A_DAC1_MUX,
1652 RT5682S_A_DACR1_SFT, rt5682s_alg_dac1_src);
1653
1654static const struct snd_kcontrol_new rt5682s_alg_dac_r1_mux =
1655 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682s_alg_dac_r1_enum);
1656
1657static const unsigned int rt5682s_adcdat_pin_values[] = {
1658 1, 3,
1659};
1660
1661static const char * const rt5682s_adcdat_pin_select[] = {
1662 "ADCDAT1", "ADCDAT2",
1663};
1664
1665static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_adcdat_pin_enum,
1666 RT5682S_GPIO_CTRL_1, RT5682S_GP4_PIN_SFT, RT5682S_GP4_PIN_MASK,
1667 rt5682s_adcdat_pin_select, rt5682s_adcdat_pin_values);
1668
1669static const struct snd_kcontrol_new rt5682s_adcdat_pin_ctrl =
1670 SOC_DAPM_ENUM("ADCDAT", rt5682s_adcdat_pin_enum);
1671
1672static const struct snd_soc_dapm_widget rt5682s_dapm_widgets[] = {
1673 SND_SOC_DAPM_SUPPLY("LDO MB1", RT5682S_PWR_ANLG_3,
1674 RT5682S_PWR_LDO_MB1_BIT, 0, NULL, 0),
1675 SND_SOC_DAPM_SUPPLY("LDO MB2", RT5682S_PWR_ANLG_3,
1676 RT5682S_PWR_LDO_MB2_BIT, 0, NULL, 0),
1677 SND_SOC_DAPM_SUPPLY("LDO", RT5682S_PWR_ANLG_3,
1678 RT5682S_PWR_LDO_BIT, 0, NULL, 0),
1679
1680 /* PLL Powers */
1681 SND_SOC_DAPM_SUPPLY_S("PLLA_LDO", 0, RT5682S_PWR_ANLG_3,
1682 RT5682S_PWR_LDO_PLLA_BIT, 0, NULL, 0),
1683 SND_SOC_DAPM_SUPPLY_S("PLLA_BIAS", 0, RT5682S_PWR_ANLG_3,
1684 RT5682S_PWR_BIAS_PLLA_BIT, 0, NULL, 0),
1685 SND_SOC_DAPM_SUPPLY_S("PLLA", 0, RT5682S_PWR_ANLG_3,
1686 RT5682S_PWR_PLLA_BIT, 0, NULL, 0),
1687 SND_SOC_DAPM_SUPPLY_S("PLLA_RST", 1, RT5682S_PWR_ANLG_3,
1688 RT5682S_RSTB_PLLA_BIT, 0, NULL, 0),
1689 SND_SOC_DAPM_SUPPLY("PLLB", SND_SOC_NOPM, 0, 0,
1690 set_pllb_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1691
1692 /* ASRC */
1693 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682S_PLL_TRACK_1,
1694 RT5682S_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1695 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682S_PLL_TRACK_1,
1696 RT5682S_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1697 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682S_PLL_TRACK_1,
1698 RT5682S_AD_ASRC_SFT, 0, NULL, 0),
1699 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682S_PLL_TRACK_1,
1700 RT5682S_DA_ASRC_SFT, 0, NULL, 0),
1701 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682S_PLL_TRACK_1,
1702 RT5682S_DMIC_ASRC_SFT, 0, NULL, 0),
1703
1704 /* Input Side */
1705 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682S_PWR_ANLG_2,
1706 RT5682S_PWR_MB1_BIT, 0, NULL, 0),
1707 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682S_PWR_ANLG_2,
1708 RT5682S_PWR_MB2_BIT, 0, NULL, 0),
1709
1710 /* Input Lines */
1711 SND_SOC_DAPM_INPUT("DMIC L1"),
1712 SND_SOC_DAPM_INPUT("DMIC R1"),
1713
1714 SND_SOC_DAPM_INPUT("IN1P"),
1715
1716 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1717 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1718 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682S_DMIC_CTRL_1, RT5682S_DMIC_1_EN_SFT, 0,
1719 set_dmic_power, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1720
1721 /* Boost */
1722 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
1723
1724 /* REC Mixer */
1725 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682s_rec1_l_mix,
1726 ARRAY_SIZE(rt5682s_rec1_l_mix)),
1727 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5682s_rec1_r_mix,
1728 ARRAY_SIZE(rt5682s_rec1_r_mix)),
1729 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682S_CAL_REC,
1730 RT5682S_PWR_RM1_L_BIT, 0, NULL, 0),
1731 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5682S_CAL_REC,
1732 RT5682S_PWR_RM1_R_BIT, 0, NULL, 0),
1733
1734 /* ADCs */
1735 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1736 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1737
1738 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682S_PWR_DIG_1,
1739 RT5682S_PWR_ADC_L1_BIT, 0, NULL, 0),
1740 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682S_PWR_DIG_1,
1741 RT5682S_PWR_ADC_R1_BIT, 0, NULL, 0),
1742 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682S_CHOP_ADC,
1743 RT5682S_CKGEN_ADC1_SFT, 0, NULL, 0),
1744
1745 /* ADC Mux */
1746 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1747 &rt5682s_sto1_adc1l_mux),
1748 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1749 &rt5682s_sto1_adc1r_mux),
1750 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1751 &rt5682s_sto1_adc2l_mux),
1752 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1753 &rt5682s_sto1_adc2r_mux),
1754 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1755 &rt5682s_sto1_adcl_mux),
1756 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1757 &rt5682s_sto1_adcr_mux),
1758 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1759 &rt5682s_if1_adc_slot_mux),
1760
1761 /* ADC Mixer */
1762 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682S_PWR_DIG_2,
1763 RT5682S_PWR_ADC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1764 SND_SOC_DAPM_MIXER_E("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1765 rt5682s_sto1_adc_l_mix, ARRAY_SIZE(rt5682s_sto1_adc_l_mix),
1766 rt5682s_stereo1_adc_mixl_event,
1767 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1768 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682S_STO1_ADC_DIG_VOL,
1769 RT5682S_R_MUTE_SFT, 1, rt5682s_sto1_adc_r_mix,
1770 ARRAY_SIZE(rt5682s_sto1_adc_r_mix)),
1771
1772 /* ADC PGA */
1773 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1774
1775 /* Digital Interface */
1776 SND_SOC_DAPM_SUPPLY("I2S1", SND_SOC_NOPM, 0, 0,
1777 set_i2s_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1778 SND_SOC_DAPM_SUPPLY("I2S2", SND_SOC_NOPM, 0, 0,
1779 set_i2s_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1780 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1781 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1782
1783 /* Digital Interface Select */
1784 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1785 &rt5682s_if1_01_adc_swap_mux),
1786 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1787 &rt5682s_if1_23_adc_swap_mux),
1788 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1789 &rt5682s_if1_45_adc_swap_mux),
1790 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1791 &rt5682s_if1_67_adc_swap_mux),
1792 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1793 &rt5682s_if2_adc_swap_mux),
1794
1795 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, &rt5682s_adcdat_pin_ctrl),
1796
1797 /* Audio Interface */
1798 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, RT5682S_I2S1_SDP,
1799 RT5682S_SEL_ADCDAT_SFT, 1),
1800 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, RT5682S_I2S2_SDP,
1801 RT5682S_I2S2_PIN_CFG_SFT, 1),
1802 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1803
1804 /* Output Side */
1805 /* DAC mixer before sound effect */
1806 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1807 rt5682s_dac_l_mix, ARRAY_SIZE(rt5682s_dac_l_mix)),
1808 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1809 rt5682s_dac_r_mix, ARRAY_SIZE(rt5682s_dac_r_mix)),
1810
1811 /* DAC channel Mux */
1812 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_l1_mux),
1813 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_r1_mux),
1814
1815 /* DAC Mixer */
1816 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682S_PWR_DIG_2,
1817 RT5682S_PWR_DAC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1818 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1819 rt5682s_sto1_dac_l_mix, ARRAY_SIZE(rt5682s_sto1_dac_l_mix)),
1820 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1821 rt5682s_sto1_dac_r_mix, ARRAY_SIZE(rt5682s_sto1_dac_r_mix)),
1822
1823 /* DACs */
1824 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_L1_BIT, 0),
1825 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_R1_BIT, 0),
1826
1827 /* HPO */
1828 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682s_hp_amp_event,
1829 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
1830
1831 /* CLK DET */
1832 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682S_CLK_DET,
1833 RT5682S_SYS_CLK_DET_SFT, 0, NULL, 0),
1834 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682S_CLK_DET,
1835 RT5682S_PLL1_CLK_DET_SFT, 0, NULL, 0),
1836 SND_SOC_DAPM_SUPPLY("MCLK0 DET PWR", RT5682S_PWR_ANLG_2,
1837 RT5682S_PWR_MCLK0_WD_BIT, 0, NULL, 0),
1838
1839 /* SAR */
1840 SND_SOC_DAPM_SUPPLY("SAR", SND_SOC_NOPM, 0, 0, sar_power_event,
1841 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1842
1843 /* Output Lines */
1844 SND_SOC_DAPM_OUTPUT("HPOL"),
1845 SND_SOC_DAPM_OUTPUT("HPOR"),
1846};
1847
1848static const struct snd_soc_dapm_route rt5682s_dapm_routes[] = {
1849 /*PLL*/
1850 {"ADC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
1851 {"ADC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
1852 {"DAC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
1853 {"DAC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
1854 {"PLLA", NULL, "PLLA_LDO"},
1855 {"PLLA", NULL, "PLLA_BIAS"},
1856 {"PLLA", NULL, "PLLA_RST"},
1857
1858 /*ASRC*/
1859 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1860 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1861 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1862 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1863 {"DAC STO1 ASRC", NULL, "AD ASRC"},
1864 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1865
1866 {"CLKDET SYS", NULL, "MCLK0 DET PWR"},
1867
1868 {"BST1 CBJ", NULL, "IN1P"},
1869 {"BST1 CBJ", NULL, "SAR"},
1870
1871 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1872 {"RECMIX1L", NULL, "RECMIX1L Power"},
1873 {"RECMIX1R", "CBJ Switch", "BST1 CBJ"},
1874 {"RECMIX1R", NULL, "RECMIX1R Power"},
1875
1876 {"ADC1 L", NULL, "RECMIX1L"},
1877 {"ADC1 L", NULL, "ADC1 L Power"},
1878 {"ADC1 L", NULL, "ADC1 clock"},
1879 {"ADC1 R", NULL, "RECMIX1R"},
1880 {"ADC1 R", NULL, "ADC1 R Power"},
1881 {"ADC1 R", NULL, "ADC1 clock"},
1882
1883 {"DMIC L1", NULL, "DMIC CLK"},
1884 {"DMIC L1", NULL, "DMIC1 Power"},
1885 {"DMIC R1", NULL, "DMIC CLK"},
1886 {"DMIC R1", NULL, "DMIC1 Power"},
1887 {"DMIC CLK", NULL, "DMIC ASRC"},
1888
1889 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1890 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1891 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1892 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1893
1894 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1895 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1896 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1897 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1898
1899 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1900 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1901 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1902 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1903
1904 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1905 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1906 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1907
1908 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1909 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1910 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1911
1912 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1913 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1914
1915 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1916 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1917 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1918 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1919 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1920 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1921 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1922 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1923 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1924 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1925 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1926 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1927 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1928 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1929 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1930 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1931
1932 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1933 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1934 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1935 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1936 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1937 {"AIF1TX", NULL, "I2S1"},
1938 {"AIF1TX", NULL, "ADCDAT Mux"},
1939 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1940 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1941 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1942 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1943 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1944 {"AIF2TX", NULL, "ADCDAT Mux"},
1945
1946 {"IF1 DAC1 L", NULL, "AIF1RX"},
1947 {"IF1 DAC1 L", NULL, "I2S1"},
1948 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1949 {"IF1 DAC1 R", NULL, "AIF1RX"},
1950 {"IF1 DAC1 R", NULL, "I2S1"},
1951 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1952
1953 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1954 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1955 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1956 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1957
1958 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1959 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1960
1961 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1962 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1963
1964 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1965 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1966 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1967 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1968
1969 {"DAC L1", NULL, "DAC L1 Source"},
1970 {"DAC R1", NULL, "DAC R1 Source"},
1971
1972 {"HP Amp", NULL, "DAC L1"},
1973 {"HP Amp", NULL, "DAC R1"},
1974 {"HP Amp", NULL, "CLKDET SYS"},
1975 {"HP Amp", NULL, "SAR"},
1976
1977 {"HPOL", NULL, "HP Amp"},
1978 {"HPOR", NULL, "HP Amp"},
1979};
1980
1981static int rt5682s_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1982 unsigned int rx_mask, int slots, int slot_width)
1983{
1984 struct snd_soc_component *component = dai->component;
1985 unsigned int cl, val = 0, tx_slotnum;
1986
1987 if (tx_mask || rx_mask)
1988 snd_soc_component_update_bits(component,
1989 RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, RT5682S_TDM_EN);
1990 else
1991 snd_soc_component_update_bits(component,
1992 RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, val: 0);
1993
1994 /* Tx slot configuration */
1995 tx_slotnum = hweight_long(w: tx_mask);
1996 if (tx_slotnum) {
1997 if (tx_slotnum > slots) {
1998 dev_err(component->dev, "Invalid or oversized Tx slots.\n");
1999 return -EINVAL;
2000 }
2001 val |= (tx_slotnum - 1) << RT5682S_TDM_ADC_DL_SFT;
2002 }
2003
2004 switch (slots) {
2005 case 4:
2006 val |= RT5682S_TDM_TX_CH_4;
2007 val |= RT5682S_TDM_RX_CH_4;
2008 break;
2009 case 6:
2010 val |= RT5682S_TDM_TX_CH_6;
2011 val |= RT5682S_TDM_RX_CH_6;
2012 break;
2013 case 8:
2014 val |= RT5682S_TDM_TX_CH_8;
2015 val |= RT5682S_TDM_RX_CH_8;
2016 break;
2017 case 2:
2018 break;
2019 default:
2020 return -EINVAL;
2021 }
2022
2023 snd_soc_component_update_bits(component, RT5682S_TDM_CTRL,
2024 RT5682S_TDM_TX_CH_MASK | RT5682S_TDM_RX_CH_MASK |
2025 RT5682S_TDM_ADC_DL_MASK, val);
2026
2027 switch (slot_width) {
2028 case 8:
2029 if (tx_mask || rx_mask)
2030 return -EINVAL;
2031 cl = RT5682S_I2S1_TX_CHL_8 | RT5682S_I2S1_RX_CHL_8;
2032 break;
2033 case 16:
2034 val = RT5682S_TDM_CL_16;
2035 cl = RT5682S_I2S1_TX_CHL_16 | RT5682S_I2S1_RX_CHL_16;
2036 break;
2037 case 20:
2038 val = RT5682S_TDM_CL_20;
2039 cl = RT5682S_I2S1_TX_CHL_20 | RT5682S_I2S1_RX_CHL_20;
2040 break;
2041 case 24:
2042 val = RT5682S_TDM_CL_24;
2043 cl = RT5682S_I2S1_TX_CHL_24 | RT5682S_I2S1_RX_CHL_24;
2044 break;
2045 case 32:
2046 val = RT5682S_TDM_CL_32;
2047 cl = RT5682S_I2S1_TX_CHL_32 | RT5682S_I2S1_RX_CHL_32;
2048 break;
2049 default:
2050 return -EINVAL;
2051 }
2052
2053 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2054 RT5682S_TDM_CL_MASK, val);
2055 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2056 RT5682S_I2S1_TX_CHL_MASK | RT5682S_I2S1_RX_CHL_MASK, val: cl);
2057
2058 return 0;
2059}
2060
2061static int rt5682s_hw_params(struct snd_pcm_substream *substream,
2062 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2063{
2064 struct snd_soc_component *component = dai->component;
2065 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
2066 unsigned int len_1 = 0, len_2 = 0;
2067 int frame_size;
2068
2069 rt5682s->lrck[dai->id] = params_rate(p: params);
2070
2071 frame_size = snd_soc_params_to_frame_size(params);
2072 if (frame_size < 0) {
2073 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
2074 return -EINVAL;
2075 }
2076
2077 switch (params_width(p: params)) {
2078 case 16:
2079 break;
2080 case 20:
2081 len_1 |= RT5682S_I2S1_DL_20;
2082 len_2 |= RT5682S_I2S2_DL_20;
2083 break;
2084 case 24:
2085 len_1 |= RT5682S_I2S1_DL_24;
2086 len_2 |= RT5682S_I2S2_DL_24;
2087 break;
2088 case 32:
2089 len_1 |= RT5682S_I2S1_DL_32;
2090 len_2 |= RT5682S_I2S2_DL_24;
2091 break;
2092 case 8:
2093 len_1 |= RT5682S_I2S2_DL_8;
2094 len_2 |= RT5682S_I2S2_DL_8;
2095 break;
2096 default:
2097 return -EINVAL;
2098 }
2099
2100 switch (dai->id) {
2101 case RT5682S_AIF1:
2102 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2103 RT5682S_I2S1_DL_MASK, val: len_1);
2104 if (params_channels(p: params) == 1) /* mono mode */
2105 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2106 RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_EN);
2107 else
2108 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2109 RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_DIS);
2110 break;
2111 case RT5682S_AIF2:
2112 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2113 RT5682S_I2S2_DL_MASK, val: len_2);
2114 if (params_channels(p: params) == 1) /* mono mode */
2115 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2116 RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_EN);
2117 else
2118 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2119 RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_DIS);
2120 break;
2121 default:
2122 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2123 return -EINVAL;
2124 }
2125
2126 return 0;
2127}
2128
2129static int rt5682s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2130{
2131 struct snd_soc_component *component = dai->component;
2132 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
2133 unsigned int reg_val = 0, tdm_ctrl = 0;
2134
2135 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2136 case SND_SOC_DAIFMT_CBP_CFP:
2137 rt5682s->master[dai->id] = 1;
2138 break;
2139 case SND_SOC_DAIFMT_CBC_CFC:
2140 rt5682s->master[dai->id] = 0;
2141 break;
2142 default:
2143 return -EINVAL;
2144 }
2145
2146 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2147 case SND_SOC_DAIFMT_NB_NF:
2148 break;
2149 case SND_SOC_DAIFMT_IB_NF:
2150 reg_val |= RT5682S_I2S_BP_INV;
2151 tdm_ctrl |= RT5682S_TDM_S_BP_INV;
2152 break;
2153 case SND_SOC_DAIFMT_NB_IF:
2154 if (dai->id == RT5682S_AIF1)
2155 tdm_ctrl |= RT5682S_TDM_S_LP_INV | RT5682S_TDM_M_BP_INV;
2156 else
2157 return -EINVAL;
2158 break;
2159 case SND_SOC_DAIFMT_IB_IF:
2160 if (dai->id == RT5682S_AIF1)
2161 tdm_ctrl |= RT5682S_TDM_S_BP_INV | RT5682S_TDM_S_LP_INV |
2162 RT5682S_TDM_M_BP_INV | RT5682S_TDM_M_LP_INV;
2163 else
2164 return -EINVAL;
2165 break;
2166 default:
2167 return -EINVAL;
2168 }
2169
2170 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2171 case SND_SOC_DAIFMT_I2S:
2172 break;
2173 case SND_SOC_DAIFMT_LEFT_J:
2174 reg_val |= RT5682S_I2S_DF_LEFT;
2175 tdm_ctrl |= RT5682S_TDM_DF_LEFT;
2176 break;
2177 case SND_SOC_DAIFMT_DSP_A:
2178 reg_val |= RT5682S_I2S_DF_PCM_A;
2179 tdm_ctrl |= RT5682S_TDM_DF_PCM_A;
2180 break;
2181 case SND_SOC_DAIFMT_DSP_B:
2182 reg_val |= RT5682S_I2S_DF_PCM_B;
2183 tdm_ctrl |= RT5682S_TDM_DF_PCM_B;
2184 break;
2185 default:
2186 return -EINVAL;
2187 }
2188
2189 switch (dai->id) {
2190 case RT5682S_AIF1:
2191 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2192 RT5682S_I2S_DF_MASK, val: reg_val);
2193 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2194 RT5682S_TDM_MS_MASK | RT5682S_TDM_S_BP_MASK |
2195 RT5682S_TDM_DF_MASK | RT5682S_TDM_M_BP_MASK |
2196 RT5682S_TDM_M_LP_MASK | RT5682S_TDM_S_LP_MASK,
2197 val: tdm_ctrl | rt5682s->master[dai->id]);
2198 break;
2199 case RT5682S_AIF2:
2200 if (rt5682s->master[dai->id] == 0)
2201 reg_val |= RT5682S_I2S2_MS_S;
2202 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2203 RT5682S_I2S2_MS_MASK | RT5682S_I2S_BP_MASK |
2204 RT5682S_I2S_DF_MASK, val: reg_val);
2205 break;
2206 default:
2207 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2208 return -EINVAL;
2209 }
2210 return 0;
2211}
2212
2213static int rt5682s_set_component_sysclk(struct snd_soc_component *component,
2214 int clk_id, int source, unsigned int freq, int dir)
2215{
2216 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
2217 unsigned int src = 0;
2218
2219 if (freq == rt5682s->sysclk && clk_id == rt5682s->sysclk_src)
2220 return 0;
2221
2222 switch (clk_id) {
2223 case RT5682S_SCLK_S_MCLK:
2224 src = RT5682S_CLK_SRC_MCLK;
2225 break;
2226 case RT5682S_SCLK_S_PLL1:
2227 src = RT5682S_CLK_SRC_PLL1;
2228 break;
2229 case RT5682S_SCLK_S_PLL2:
2230 src = RT5682S_CLK_SRC_PLL2;
2231 break;
2232 case RT5682S_SCLK_S_RCCLK:
2233 src = RT5682S_CLK_SRC_RCCLK;
2234 break;
2235 default:
2236 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2237 return -EINVAL;
2238 }
2239
2240 snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2241 RT5682S_SCLK_SRC_MASK, val: src << RT5682S_SCLK_SRC_SFT);
2242 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1,
2243 RT5682S_I2S_M_CLK_SRC_MASK, val: src << RT5682S_I2S_M_CLK_SRC_SFT);
2244 snd_soc_component_update_bits(component, RT5682S_I2S2_M_CLK_CTRL_1,
2245 RT5682S_I2S2_M_CLK_SRC_MASK, val: src << RT5682S_I2S2_M_CLK_SRC_SFT);
2246
2247 rt5682s->sysclk = freq;
2248 rt5682s->sysclk_src = clk_id;
2249
2250 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2251 freq, clk_id);
2252
2253 return 0;
2254}
2255
2256static const struct pll_calc_map plla_table[] = {
2257 {2048000, 24576000, 0, 46, 2, true, false, false, false},
2258 {256000, 24576000, 0, 382, 2, true, false, false, false},
2259 {512000, 24576000, 0, 190, 2, true, false, false, false},
2260 {4096000, 24576000, 0, 22, 2, true, false, false, false},
2261 {1024000, 24576000, 0, 94, 2, true, false, false, false},
2262 {11289600, 22579200, 1, 22, 2, false, false, false, false},
2263 {1411200, 22579200, 0, 62, 2, true, false, false, false},
2264 {2822400, 22579200, 0, 30, 2, true, false, false, false},
2265 {12288000, 24576000, 1, 22, 2, false, false, false, false},
2266 {1536000, 24576000, 0, 62, 2, true, false, false, false},
2267 {3072000, 24576000, 0, 30, 2, true, false, false, false},
2268 {24576000, 49152000, 4, 22, 0, false, false, false, false},
2269 {3072000, 49152000, 0, 30, 0, true, false, false, false},
2270 {6144000, 49152000, 0, 30, 0, false, false, false, false},
2271 {49152000, 98304000, 10, 22, 0, false, true, false, false},
2272 {6144000, 98304000, 0, 30, 0, false, true, false, false},
2273 {12288000, 98304000, 1, 22, 0, false, true, false, false},
2274 {48000000, 3840000, 10, 22, 23, false, false, false, false},
2275 {24000000, 3840000, 4, 22, 23, false, false, false, false},
2276 {19200000, 3840000, 3, 23, 23, false, false, false, false},
2277 {38400000, 3840000, 8, 23, 23, false, false, false, false},
2278};
2279
2280static const struct pll_calc_map pllb_table[] = {
2281 {48000000, 24576000, 8, 6, 3, false, false, false, false},
2282 {48000000, 22579200, 23, 12, 3, false, false, false, true},
2283 {24000000, 24576000, 3, 6, 3, false, false, false, false},
2284 {24000000, 22579200, 23, 26, 3, false, false, false, true},
2285 {19200000, 24576000, 2, 6, 3, false, false, false, false},
2286 {19200000, 22579200, 3, 5, 3, false, false, false, true},
2287 {38400000, 24576000, 6, 6, 3, false, false, false, false},
2288 {38400000, 22579200, 8, 5, 3, false, false, false, true},
2289 {3840000, 49152000, 0, 6, 0, true, false, false, false},
2290};
2291
2292static int find_pll_inter_combination(unsigned int f_in, unsigned int f_out,
2293 struct pll_calc_map *a, struct pll_calc_map *b)
2294{
2295 int i, j;
2296
2297 /* Look at PLLA table */
2298 for (i = 0; i < ARRAY_SIZE(plla_table); i++) {
2299 if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == f_out) {
2300 memcpy(a, plla_table + i, sizeof(*a));
2301 return USE_PLLA;
2302 }
2303 }
2304
2305 /* Look at PLLB table */
2306 for (i = 0; i < ARRAY_SIZE(pllb_table); i++) {
2307 if (pllb_table[i].freq_in == f_in && pllb_table[i].freq_out == f_out) {
2308 memcpy(b, pllb_table + i, sizeof(*b));
2309 return USE_PLLB;
2310 }
2311 }
2312
2313 /* Find a combination of PLLA & PLLB */
2314 for (i = ARRAY_SIZE(plla_table) - 1; i >= 0; i--) {
2315 if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == 3840000) {
2316 for (j = ARRAY_SIZE(pllb_table) - 1; j >= 0; j--) {
2317 if (pllb_table[j].freq_in == 3840000 &&
2318 pllb_table[j].freq_out == f_out) {
2319 memcpy(a, plla_table + i, sizeof(*a));
2320 memcpy(b, pllb_table + j, sizeof(*b));
2321 return USE_PLLAB;
2322 }
2323 }
2324 }
2325 }
2326
2327 return -EINVAL;
2328}
2329
2330static int rt5682s_set_component_pll(struct snd_soc_component *component,
2331 int pll_id, int source, unsigned int freq_in,
2332 unsigned int freq_out)
2333{
2334 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
2335 struct pll_calc_map a_map, b_map;
2336
2337 if (source == rt5682s->pll_src[pll_id] && freq_in == rt5682s->pll_in[pll_id] &&
2338 freq_out == rt5682s->pll_out[pll_id])
2339 return 0;
2340
2341 if (!freq_in || !freq_out) {
2342 dev_dbg(component->dev, "PLL disabled\n");
2343 rt5682s->pll_in[pll_id] = 0;
2344 rt5682s->pll_out[pll_id] = 0;
2345 snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2346 RT5682S_SCLK_SRC_MASK, RT5682S_CLK_SRC_MCLK << RT5682S_SCLK_SRC_SFT);
2347 return 0;
2348 }
2349
2350 switch (source) {
2351 case RT5682S_PLL_S_MCLK:
2352 snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2353 RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_MCLK);
2354 break;
2355 case RT5682S_PLL_S_BCLK1:
2356 snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2357 RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_BCLK1);
2358 break;
2359 default:
2360 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2361 return -EINVAL;
2362 }
2363
2364 rt5682s->pll_comb = find_pll_inter_combination(f_in: freq_in, f_out: freq_out,
2365 a: &a_map, b: &b_map);
2366
2367 if ((pll_id == RT5682S_PLL1 && rt5682s->pll_comb == USE_PLLA) ||
2368 (pll_id == RT5682S_PLL2 && (rt5682s->pll_comb == USE_PLLB ||
2369 rt5682s->pll_comb == USE_PLLAB))) {
2370 dev_dbg(component->dev,
2371 "Supported freq conversion for PLL%d:(%d->%d): %d\n",
2372 pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
2373 } else {
2374 dev_err(component->dev,
2375 "Unsupported freq conversion for PLL%d:(%d->%d): %d\n",
2376 pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
2377 return -EINVAL;
2378 }
2379
2380 if (rt5682s->pll_comb == USE_PLLA || rt5682s->pll_comb == USE_PLLAB) {
2381 dev_dbg(component->dev,
2382 "PLLA: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d\n",
2383 a_map.freq_in, a_map.freq_out, a_map.m_bp, a_map.k_bp,
2384 (a_map.m_bp ? 0 : a_map.m), a_map.n, (a_map.k_bp ? 0 : a_map.k));
2385 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_1,
2386 RT5682S_PLLA_N_MASK, val: a_map.n);
2387 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_2,
2388 RT5682S_PLLA_M_MASK | RT5682S_PLLA_K_MASK,
2389 val: a_map.m << RT5682S_PLLA_M_SFT | a_map.k);
2390 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6,
2391 RT5682S_PLLA_M_BP_MASK | RT5682S_PLLA_K_BP_MASK,
2392 val: a_map.m_bp << RT5682S_PLLA_M_BP_SFT |
2393 a_map.k_bp << RT5682S_PLLA_K_BP_SFT);
2394 }
2395
2396 if (rt5682s->pll_comb == USE_PLLB || rt5682s->pll_comb == USE_PLLAB) {
2397 dev_dbg(component->dev,
2398 "PLLB: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d byp_ps=%d sel_ps=%d\n",
2399 b_map.freq_in, b_map.freq_out, b_map.m_bp, b_map.k_bp,
2400 (b_map.m_bp ? 0 : b_map.m), b_map.n, (b_map.k_bp ? 0 : b_map.k),
2401 b_map.byp_ps, b_map.sel_ps);
2402 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_3,
2403 RT5682S_PLLB_N_MASK, val: b_map.n);
2404 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_4,
2405 RT5682S_PLLB_M_MASK | RT5682S_PLLB_K_MASK,
2406 val: b_map.m << RT5682S_PLLB_M_SFT | b_map.k);
2407 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6,
2408 RT5682S_PLLB_SEL_PS_MASK | RT5682S_PLLB_BYP_PS_MASK |
2409 RT5682S_PLLB_M_BP_MASK | RT5682S_PLLB_K_BP_MASK,
2410 val: b_map.sel_ps << RT5682S_PLLB_SEL_PS_SFT |
2411 b_map.byp_ps << RT5682S_PLLB_BYP_PS_SFT |
2412 b_map.m_bp << RT5682S_PLLB_M_BP_SFT |
2413 b_map.k_bp << RT5682S_PLLB_K_BP_SFT);
2414 }
2415
2416 if (rt5682s->pll_comb == USE_PLLB)
2417 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_7,
2418 RT5682S_PLLB_SRC_MASK, RT5682S_PLLB_SRC_DFIN);
2419
2420 rt5682s->pll_in[pll_id] = freq_in;
2421 rt5682s->pll_out[pll_id] = freq_out;
2422 rt5682s->pll_src[pll_id] = source;
2423
2424 return 0;
2425}
2426
2427static int rt5682s_set_bclk1_ratio(struct snd_soc_dai *dai,
2428 unsigned int ratio)
2429{
2430 struct snd_soc_component *component = dai->component;
2431 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
2432
2433 rt5682s->bclk[dai->id] = ratio;
2434
2435 switch (ratio) {
2436 case 256:
2437 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2438 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_256);
2439 break;
2440 case 128:
2441 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2442 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_128);
2443 break;
2444 case 64:
2445 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2446 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_64);
2447 break;
2448 case 32:
2449 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2450 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_32);
2451 break;
2452 default:
2453 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2454 return -EINVAL;
2455 }
2456
2457 return 0;
2458}
2459
2460static int rt5682s_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2461{
2462 struct snd_soc_component *component = dai->component;
2463 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
2464
2465 rt5682s->bclk[dai->id] = ratio;
2466
2467 switch (ratio) {
2468 case 64:
2469 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2,
2470 RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_64);
2471 break;
2472 case 32:
2473 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2,
2474 RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_32);
2475 break;
2476 default:
2477 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2478 return -EINVAL;
2479 }
2480
2481 return 0;
2482}
2483
2484static int rt5682s_set_bias_level(struct snd_soc_component *component,
2485 enum snd_soc_bias_level level)
2486{
2487 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
2488 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
2489
2490 switch (level) {
2491 case SND_SOC_BIAS_PREPARE:
2492 regmap_update_bits(map: rt5682s->regmap, RT5682S_PWR_DIG_1,
2493 RT5682S_PWR_LDO, RT5682S_PWR_LDO);
2494 break;
2495 case SND_SOC_BIAS_STANDBY:
2496 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF)
2497 regmap_update_bits(map: rt5682s->regmap, RT5682S_PWR_DIG_1,
2498 RT5682S_DIG_GATE_CTRL, RT5682S_DIG_GATE_CTRL);
2499 break;
2500 case SND_SOC_BIAS_OFF:
2501 regmap_update_bits(map: rt5682s->regmap, RT5682S_PWR_DIG_1, RT5682S_PWR_LDO, val: 0);
2502 if (!rt5682s->wclk_enabled)
2503 regmap_update_bits(map: rt5682s->regmap, RT5682S_PWR_DIG_1,
2504 RT5682S_DIG_GATE_CTRL, val: 0);
2505 break;
2506 case SND_SOC_BIAS_ON:
2507 break;
2508 }
2509
2510 return 0;
2511}
2512
2513#ifdef CONFIG_COMMON_CLK
2514#define CLK_PLL2_FIN 48000000
2515#define CLK_48 48000
2516#define CLK_44 44100
2517
2518static bool rt5682s_clk_check(struct rt5682s_priv *rt5682s)
2519{
2520 if (!rt5682s->master[RT5682S_AIF1]) {
2521 dev_dbg(rt5682s->component->dev, "dai clk fmt not set correctly\n");
2522 return false;
2523 }
2524 return true;
2525}
2526
2527static int rt5682s_wclk_prepare(struct clk_hw *hw)
2528{
2529 struct rt5682s_priv *rt5682s =
2530 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2531 struct snd_soc_component *component = rt5682s->component;
2532 int ref, reg;
2533
2534 if (!rt5682s_clk_check(rt5682s))
2535 return -EINVAL;
2536
2537 mutex_lock(&rt5682s->wclk_mutex);
2538
2539 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2540 RT5682S_PWR_VREF2 | RT5682S_PWR_FV2 | RT5682S_PWR_MB,
2541 RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
2542 usleep_range(min: 15000, max: 20000);
2543 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2544 RT5682S_PWR_FV2, RT5682S_PWR_FV2);
2545
2546 /* Set and power on I2S1 */
2547 snd_soc_component_update_bits(component, RT5682S_PWR_DIG_1,
2548 RT5682S_DIG_GATE_CTRL, RT5682S_DIG_GATE_CTRL);
2549 rt5682s_set_i2s(rt5682s, id: RT5682S_AIF1, on: 1);
2550
2551 /* Only need to power on PLLB due to the rate set restriction */
2552 reg = RT5682S_PLL_TRACK_2;
2553 ref = 256 * rt5682s->lrck[RT5682S_AIF1];
2554 rt5682s_set_filter_clk(rt5682s, reg, ref);
2555 rt5682s_set_pllb_power(rt5682s, on: 1);
2556
2557 rt5682s->wclk_enabled = 1;
2558
2559 mutex_unlock(lock: &rt5682s->wclk_mutex);
2560
2561 return 0;
2562}
2563
2564static void rt5682s_wclk_unprepare(struct clk_hw *hw)
2565{
2566 struct rt5682s_priv *rt5682s =
2567 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2568 struct snd_soc_component *component = rt5682s->component;
2569
2570 if (!rt5682s_clk_check(rt5682s))
2571 return;
2572
2573 mutex_lock(&rt5682s->wclk_mutex);
2574
2575 if (!rt5682s->jack_type)
2576 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2577 RT5682S_PWR_VREF2 | RT5682S_PWR_FV2 | RT5682S_PWR_MB, val: 0);
2578
2579 /* Power down I2S1 */
2580 rt5682s_set_i2s(rt5682s, id: RT5682S_AIF1, on: 0);
2581 snd_soc_component_update_bits(component, RT5682S_PWR_DIG_1,
2582 RT5682S_DIG_GATE_CTRL, val: 0);
2583
2584 /* Power down PLLB */
2585 rt5682s_set_pllb_power(rt5682s, on: 0);
2586
2587 rt5682s->wclk_enabled = 0;
2588
2589 mutex_unlock(lock: &rt5682s->wclk_mutex);
2590}
2591
2592static unsigned long rt5682s_wclk_recalc_rate(struct clk_hw *hw,
2593 unsigned long parent_rate)
2594{
2595 struct rt5682s_priv *rt5682s =
2596 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2597 struct snd_soc_component *component = rt5682s->component;
2598 const char * const clk_name = clk_hw_get_name(hw);
2599
2600 if (!rt5682s_clk_check(rt5682s))
2601 return 0;
2602 /*
2603 * Only accept to set wclk rate to 44.1k or 48kHz.
2604 */
2605 if (rt5682s->lrck[RT5682S_AIF1] != CLK_48 &&
2606 rt5682s->lrck[RT5682S_AIF1] != CLK_44) {
2607 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2608 __func__, clk_name, CLK_44, CLK_48);
2609 return 0;
2610 }
2611
2612 return rt5682s->lrck[RT5682S_AIF1];
2613}
2614
2615static int rt5682s_wclk_determine_rate(struct clk_hw *hw,
2616 struct clk_rate_request *req)
2617{
2618 struct rt5682s_priv *rt5682s =
2619 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2620 struct snd_soc_component *component = rt5682s->component;
2621 const char * const clk_name = clk_hw_get_name(hw);
2622
2623 if (!rt5682s_clk_check(rt5682s))
2624 return -EINVAL;
2625 /*
2626 * Only accept to set wclk rate to 44.1k or 48kHz.
2627 * It will force to 48kHz if not both.
2628 */
2629 if (req->rate != CLK_48 && req->rate != CLK_44) {
2630 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2631 __func__, clk_name, CLK_44, CLK_48);
2632 req->rate = CLK_48;
2633 }
2634
2635 return 0;
2636}
2637
2638static int rt5682s_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2639 unsigned long parent_rate)
2640{
2641 struct rt5682s_priv *rt5682s =
2642 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2643 struct snd_soc_component *component = rt5682s->component;
2644 struct clk *parent_clk;
2645 const char * const clk_name = clk_hw_get_name(hw);
2646 unsigned int clk_pll2_fout;
2647
2648 if (!rt5682s_clk_check(rt5682s))
2649 return -EINVAL;
2650
2651 /*
2652 * Whether the wclk's parent clk (mclk) exists or not, please ensure
2653 * it is fixed or set to 48MHz before setting wclk rate. It's a
2654 * temporary limitation. Only accept 48MHz clk as the clk provider.
2655 *
2656 * It will set the codec anyway by assuming mclk is 48MHz.
2657 */
2658 parent_clk = clk_get_parent(clk: hw->clk);
2659 if (!parent_clk)
2660 dev_warn(component->dev,
2661 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2662 CLK_PLL2_FIN);
2663
2664 if (parent_rate != CLK_PLL2_FIN)
2665 dev_warn(component->dev, "clk %s only support %d Hz input\n",
2666 clk_name, CLK_PLL2_FIN);
2667
2668 /*
2669 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2670 * PLL2 is needed.
2671 */
2672 clk_pll2_fout = rate * 512;
2673 rt5682s_set_component_pll(component, pll_id: RT5682S_PLL2, source: RT5682S_PLL_S_MCLK,
2674 CLK_PLL2_FIN, freq_out: clk_pll2_fout);
2675
2676 rt5682s_set_component_sysclk(component, clk_id: RT5682S_SCLK_S_PLL2, source: 0,
2677 freq: clk_pll2_fout, SND_SOC_CLOCK_IN);
2678
2679 rt5682s->lrck[RT5682S_AIF1] = rate;
2680
2681 return 0;
2682}
2683
2684static unsigned long rt5682s_bclk_recalc_rate(struct clk_hw *hw,
2685 unsigned long parent_rate)
2686{
2687 struct rt5682s_priv *rt5682s =
2688 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2689 struct snd_soc_component *component = rt5682s->component;
2690 unsigned int bclks_per_wclk;
2691
2692 bclks_per_wclk = snd_soc_component_read(component, RT5682S_TDM_TCON_CTRL_1);
2693
2694 switch (bclks_per_wclk & RT5682S_TDM_BCLK_MS1_MASK) {
2695 case RT5682S_TDM_BCLK_MS1_256:
2696 return parent_rate * 256;
2697 case RT5682S_TDM_BCLK_MS1_128:
2698 return parent_rate * 128;
2699 case RT5682S_TDM_BCLK_MS1_64:
2700 return parent_rate * 64;
2701 case RT5682S_TDM_BCLK_MS1_32:
2702 return parent_rate * 32;
2703 default:
2704 return 0;
2705 }
2706}
2707
2708static unsigned long rt5682s_bclk_get_factor(unsigned long rate,
2709 unsigned long parent_rate)
2710{
2711 unsigned long factor;
2712
2713 factor = rate / parent_rate;
2714 if (factor < 64)
2715 return 32;
2716 else if (factor < 128)
2717 return 64;
2718 else if (factor < 256)
2719 return 128;
2720 else
2721 return 256;
2722}
2723
2724static int rt5682s_bclk_determine_rate(struct clk_hw *hw,
2725 struct clk_rate_request *req)
2726{
2727 struct rt5682s_priv *rt5682s =
2728 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2729 unsigned long factor;
2730
2731 if (!req->best_parent_rate || !rt5682s_clk_check(rt5682s))
2732 return -EINVAL;
2733
2734 /*
2735 * BCLK rates are set as a multiplier of WCLK in HW.
2736 * We don't allow changing the parent WCLK. We just do
2737 * some rounding down based on the parent WCLK rate
2738 * and find the appropriate multiplier of BCLK to
2739 * get the rounded down BCLK value.
2740 */
2741 factor = rt5682s_bclk_get_factor(rate: req->rate, parent_rate: req->best_parent_rate);
2742
2743 req->rate = req->best_parent_rate * factor;
2744
2745 return 0;
2746}
2747
2748static int rt5682s_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2749 unsigned long parent_rate)
2750{
2751 struct rt5682s_priv *rt5682s =
2752 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2753 struct snd_soc_component *component = rt5682s->component;
2754 struct snd_soc_dai *dai;
2755 unsigned long factor;
2756
2757 if (!rt5682s_clk_check(rt5682s))
2758 return -EINVAL;
2759
2760 factor = rt5682s_bclk_get_factor(rate, parent_rate);
2761
2762 for_each_component_dais(component, dai)
2763 if (dai->id == RT5682S_AIF1)
2764 return rt5682s_set_bclk1_ratio(dai, ratio: factor);
2765
2766 dev_err(component->dev, "dai %d not found in component\n",
2767 RT5682S_AIF1);
2768 return -ENODEV;
2769}
2770
2771static const struct clk_ops rt5682s_dai_clk_ops[RT5682S_DAI_NUM_CLKS] = {
2772 [RT5682S_DAI_WCLK_IDX] = {
2773 .prepare = rt5682s_wclk_prepare,
2774 .unprepare = rt5682s_wclk_unprepare,
2775 .recalc_rate = rt5682s_wclk_recalc_rate,
2776 .determine_rate = rt5682s_wclk_determine_rate,
2777 .set_rate = rt5682s_wclk_set_rate,
2778 },
2779 [RT5682S_DAI_BCLK_IDX] = {
2780 .recalc_rate = rt5682s_bclk_recalc_rate,
2781 .determine_rate = rt5682s_bclk_determine_rate,
2782 .set_rate = rt5682s_bclk_set_rate,
2783 },
2784};
2785
2786static int rt5682s_register_dai_clks(struct snd_soc_component *component)
2787{
2788 struct device *dev = component->dev;
2789 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
2790 struct rt5682s_platform_data *pdata = &rt5682s->pdata;
2791 struct clk_hw *dai_clk_hw;
2792 int i, ret;
2793
2794 for (i = 0; i < RT5682S_DAI_NUM_CLKS; ++i) {
2795 struct clk_init_data init = { };
2796 struct clk_parent_data parent_data;
2797 const struct clk_hw *parent;
2798
2799 dai_clk_hw = &rt5682s->dai_clks_hw[i];
2800
2801 switch (i) {
2802 case RT5682S_DAI_WCLK_IDX:
2803 /* Make MCLK the parent of WCLK */
2804 if (rt5682s->mclk) {
2805 parent_data = (struct clk_parent_data){
2806 .fw_name = "mclk",
2807 };
2808 init.parent_data = &parent_data;
2809 init.num_parents = 1;
2810 }
2811 break;
2812 case RT5682S_DAI_BCLK_IDX:
2813 /* Make WCLK the parent of BCLK */
2814 parent = &rt5682s->dai_clks_hw[RT5682S_DAI_WCLK_IDX];
2815 init.parent_hws = &parent;
2816 init.num_parents = 1;
2817 break;
2818 default:
2819 dev_err(dev, "Invalid clock index\n");
2820 return -EINVAL;
2821 }
2822
2823 init.name = pdata->dai_clk_names[i];
2824 init.ops = &rt5682s_dai_clk_ops[i];
2825 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2826 dai_clk_hw->init = &init;
2827
2828 ret = devm_clk_hw_register(dev, hw: dai_clk_hw);
2829 if (ret) {
2830 dev_warn(dev, "Failed to register %s: %d\n", init.name, ret);
2831 return ret;
2832 }
2833
2834 if (dev->of_node) {
2835 ret = devm_of_clk_add_hw_provider(dev, get: of_clk_hw_simple_get, data: dai_clk_hw);
2836 if (ret)
2837 return ret;
2838 } else {
2839 ret = devm_clk_hw_register_clkdev(dev, hw: dai_clk_hw,
2840 con_id: init.name, dev_id: dev_name(dev));
2841 if (ret)
2842 return ret;
2843 }
2844 }
2845
2846 return 0;
2847}
2848
2849static int rt5682s_dai_probe_clks(struct snd_soc_component *component)
2850{
2851 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
2852 int ret;
2853
2854 /* Check if MCLK provided */
2855 rt5682s->mclk = devm_clk_get_optional(dev: component->dev, id: "mclk");
2856 if (IS_ERR(ptr: rt5682s->mclk))
2857 return PTR_ERR(ptr: rt5682s->mclk);
2858
2859 /* Register CCF DAI clock control */
2860 ret = rt5682s_register_dai_clks(component);
2861 if (ret)
2862 return ret;
2863
2864 /* Initial setup for CCF */
2865 rt5682s->lrck[RT5682S_AIF1] = CLK_48;
2866
2867 return 0;
2868}
2869#else
2870static inline int rt5682s_dai_probe_clks(struct snd_soc_component *component)
2871{
2872 return 0;
2873}
2874#endif /* CONFIG_COMMON_CLK */
2875
2876static int rt5682s_probe(struct snd_soc_component *component)
2877{
2878 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
2879
2880 rt5682s->component = component;
2881
2882 return rt5682s_dai_probe_clks(component);
2883}
2884
2885static void rt5682s_remove(struct snd_soc_component *component)
2886{
2887 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
2888
2889 rt5682s_reset(rt5682s);
2890}
2891
2892#ifdef CONFIG_PM
2893static int rt5682s_suspend(struct snd_soc_component *component)
2894{
2895 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
2896
2897 if (rt5682s->irq)
2898 disable_irq(irq: rt5682s->irq);
2899
2900 cancel_delayed_work_sync(dwork: &rt5682s->jack_detect_work);
2901 cancel_delayed_work_sync(dwork: &rt5682s->jd_check_work);
2902
2903 if (rt5682s->hs_jack)
2904 rt5682s->jack_type = rt5682s_headset_detect(component, jack_insert: 0);
2905
2906 regcache_cache_only(map: rt5682s->regmap, enable: true);
2907 regcache_mark_dirty(map: rt5682s->regmap);
2908
2909 return 0;
2910}
2911
2912static int rt5682s_resume(struct snd_soc_component *component)
2913{
2914 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(c: component);
2915
2916 regcache_cache_only(map: rt5682s->regmap, enable: false);
2917 regcache_sync(map: rt5682s->regmap);
2918
2919 if (rt5682s->hs_jack) {
2920 mod_delayed_work(wq: system_power_efficient_wq,
2921 dwork: &rt5682s->jack_detect_work, delay: msecs_to_jiffies(m: 0));
2922 }
2923
2924 if (rt5682s->irq)
2925 enable_irq(irq: rt5682s->irq);
2926
2927 return 0;
2928}
2929#else
2930#define rt5682s_suspend NULL
2931#define rt5682s_resume NULL
2932#endif
2933
2934static const struct snd_soc_dai_ops rt5682s_aif1_dai_ops = {
2935 .hw_params = rt5682s_hw_params,
2936 .set_fmt = rt5682s_set_dai_fmt,
2937 .set_tdm_slot = rt5682s_set_tdm_slot,
2938 .set_bclk_ratio = rt5682s_set_bclk1_ratio,
2939};
2940
2941static const struct snd_soc_dai_ops rt5682s_aif2_dai_ops = {
2942 .hw_params = rt5682s_hw_params,
2943 .set_fmt = rt5682s_set_dai_fmt,
2944 .set_bclk_ratio = rt5682s_set_bclk2_ratio,
2945};
2946
2947static const struct snd_soc_component_driver rt5682s_soc_component_dev = {
2948 .probe = rt5682s_probe,
2949 .remove = rt5682s_remove,
2950 .suspend = rt5682s_suspend,
2951 .resume = rt5682s_resume,
2952 .set_bias_level = rt5682s_set_bias_level,
2953 .controls = rt5682s_snd_controls,
2954 .num_controls = ARRAY_SIZE(rt5682s_snd_controls),
2955 .dapm_widgets = rt5682s_dapm_widgets,
2956 .num_dapm_widgets = ARRAY_SIZE(rt5682s_dapm_widgets),
2957 .dapm_routes = rt5682s_dapm_routes,
2958 .num_dapm_routes = ARRAY_SIZE(rt5682s_dapm_routes),
2959 .set_sysclk = rt5682s_set_component_sysclk,
2960 .set_pll = rt5682s_set_component_pll,
2961 .set_jack = rt5682s_set_jack_detect,
2962 .use_pmdown_time = 1,
2963 .endianness = 1,
2964};
2965
2966static int rt5682s_parse_dt(struct rt5682s_priv *rt5682s, struct device *dev)
2967{
2968 device_property_read_u32(dev, propname: "realtek,dmic1-data-pin",
2969 val: &rt5682s->pdata.dmic1_data_pin);
2970 device_property_read_u32(dev, propname: "realtek,dmic1-clk-pin",
2971 val: &rt5682s->pdata.dmic1_clk_pin);
2972 device_property_read_u32(dev, propname: "realtek,jd-src",
2973 val: &rt5682s->pdata.jd_src);
2974 device_property_read_u32(dev, propname: "realtek,dmic-clk-rate-hz",
2975 val: &rt5682s->pdata.dmic_clk_rate);
2976 device_property_read_u32(dev, propname: "realtek,dmic-delay-ms",
2977 val: &rt5682s->pdata.dmic_delay);
2978 device_property_read_u32(dev, propname: "realtek,amic-delay-ms",
2979 val: &rt5682s->pdata.amic_delay);
2980 device_property_read_u32(dev, propname: "realtek,ldo-sel",
2981 val: &rt5682s->pdata.ldo_dacref);
2982
2983 if (device_property_read_string_array(dev, propname: "clock-output-names",
2984 val: rt5682s->pdata.dai_clk_names,
2985 nval: RT5682S_DAI_NUM_CLKS) < 0)
2986 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
2987 rt5682s->pdata.dai_clk_names[RT5682S_DAI_WCLK_IDX],
2988 rt5682s->pdata.dai_clk_names[RT5682S_DAI_BCLK_IDX]);
2989
2990 rt5682s->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
2991 propname: "realtek,dmic-clk-driving-high");
2992
2993 return 0;
2994}
2995
2996static void rt5682s_calibrate(struct rt5682s_priv *rt5682s)
2997{
2998 unsigned int count, value;
2999
3000 mutex_lock(&rt5682s->calibrate_mutex);
3001
3002 regmap_write(map: rt5682s->regmap, RT5682S_PWR_ANLG_1, val: 0xaa80);
3003 usleep_range(min: 15000, max: 20000);
3004 regmap_write(map: rt5682s->regmap, RT5682S_PWR_ANLG_1, val: 0xfa80);
3005 regmap_write(map: rt5682s->regmap, RT5682S_PWR_DIG_1, val: 0x01c0);
3006 regmap_write(map: rt5682s->regmap, RT5682S_MICBIAS_2, val: 0x0380);
3007 regmap_write(map: rt5682s->regmap, RT5682S_GLB_CLK, val: 0x8000);
3008 regmap_write(map: rt5682s->regmap, RT5682S_ADDA_CLK_1, val: 0x1001);
3009 regmap_write(map: rt5682s->regmap, RT5682S_CHOP_DAC_2, val: 0x3030);
3010 regmap_write(map: rt5682s->regmap, RT5682S_CHOP_ADC, val: 0xb000);
3011 regmap_write(map: rt5682s->regmap, RT5682S_STO1_ADC_MIXER, val: 0x686c);
3012 regmap_write(map: rt5682s->regmap, RT5682S_CAL_REC, val: 0x5151);
3013 regmap_write(map: rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, val: 0x0321);
3014 regmap_write(map: rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2, val: 0x0004);
3015 regmap_write(map: rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, val: 0x7c00);
3016 regmap_write(map: rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, val: 0xfc00);
3017
3018 for (count = 0; count < 60; count++) {
3019 regmap_read(map: rt5682s->regmap, RT5682S_HP_CALIB_ST_1, val: &value);
3020 if (!(value & 0x8000))
3021 break;
3022
3023 usleep_range(min: 10000, max: 10005);
3024 }
3025
3026 if (count >= 60)
3027 dev_err(rt5682s->component->dev, "HP Calibration Failure\n");
3028
3029 /* restore settings */
3030 regmap_write(map: rt5682s->regmap, RT5682S_MICBIAS_2, val: 0x0180);
3031 regmap_write(map: rt5682s->regmap, RT5682S_CAL_REC, val: 0x5858);
3032 regmap_write(map: rt5682s->regmap, RT5682S_STO1_ADC_MIXER, val: 0xc0c4);
3033 regmap_write(map: rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, val: 0x0320);
3034 regmap_write(map: rt5682s->regmap, RT5682S_PWR_DIG_1, val: 0x00c0);
3035 regmap_write(map: rt5682s->regmap, RT5682S_PWR_ANLG_1, val: 0x0800);
3036 regmap_write(map: rt5682s->regmap, RT5682S_GLB_CLK, val: 0x0000);
3037
3038 mutex_unlock(lock: &rt5682s->calibrate_mutex);
3039}
3040
3041static const struct regmap_config rt5682s_regmap = {
3042 .reg_bits = 16,
3043 .val_bits = 16,
3044 .max_register = RT5682S_MAX_REG,
3045 .volatile_reg = rt5682s_volatile_register,
3046 .readable_reg = rt5682s_readable_register,
3047 .cache_type = REGCACHE_MAPLE,
3048 .reg_defaults = rt5682s_reg,
3049 .num_reg_defaults = ARRAY_SIZE(rt5682s_reg),
3050 .use_single_read = true,
3051 .use_single_write = true,
3052};
3053
3054static struct snd_soc_dai_driver rt5682s_dai[] = {
3055 {
3056 .name = "rt5682s-aif1",
3057 .id = RT5682S_AIF1,
3058 .playback = {
3059 .stream_name = "AIF1 Playback",
3060 .channels_min = 1,
3061 .channels_max = 2,
3062 .rates = RT5682S_STEREO_RATES,
3063 .formats = RT5682S_FORMATS,
3064 },
3065 .capture = {
3066 .stream_name = "AIF1 Capture",
3067 .channels_min = 1,
3068 .channels_max = 2,
3069 .rates = RT5682S_STEREO_RATES,
3070 .formats = RT5682S_FORMATS,
3071 },
3072 .ops = &rt5682s_aif1_dai_ops,
3073 },
3074 {
3075 .name = "rt5682s-aif2",
3076 .id = RT5682S_AIF2,
3077 .capture = {
3078 .stream_name = "AIF2 Capture",
3079 .channels_min = 1,
3080 .channels_max = 2,
3081 .rates = RT5682S_STEREO_RATES,
3082 .formats = RT5682S_FORMATS,
3083 },
3084 .ops = &rt5682s_aif2_dai_ops,
3085 },
3086};
3087
3088static void rt5682s_i2c_disable_regulators(void *data)
3089{
3090 struct rt5682s_priv *rt5682s = data;
3091 struct device *dev = regmap_get_device(map: rt5682s->regmap);
3092 int ret;
3093
3094 ret = regulator_disable(regulator: rt5682s->supplies[RT5682S_SUPPLY_AVDD].consumer);
3095 if (ret)
3096 dev_err(dev, "Failed to disable supply AVDD: %d\n", ret);
3097
3098 ret = regulator_disable(regulator: rt5682s->supplies[RT5682S_SUPPLY_DBVDD].consumer);
3099 if (ret)
3100 dev_err(dev, "Failed to disable supply DBVDD: %d\n", ret);
3101
3102 ret = regulator_disable(regulator: rt5682s->supplies[RT5682S_SUPPLY_LDO1_IN].consumer);
3103 if (ret)
3104 dev_err(dev, "Failed to disable supply LDO1-IN: %d\n", ret);
3105
3106 usleep_range(min: 1000, max: 1500);
3107
3108 ret = regulator_disable(regulator: rt5682s->supplies[RT5682S_SUPPLY_MICVDD].consumer);
3109 if (ret)
3110 dev_err(dev, "Failed to disable supply MICVDD: %d\n", ret);
3111}
3112
3113static int rt5682s_i2c_probe(struct i2c_client *i2c)
3114{
3115 struct rt5682s_platform_data *pdata = dev_get_platdata(dev: &i2c->dev);
3116 struct rt5682s_priv *rt5682s;
3117 int i, ret;
3118 unsigned int val;
3119
3120 rt5682s = devm_kzalloc(dev: &i2c->dev, size: sizeof(struct rt5682s_priv), GFP_KERNEL);
3121 if (!rt5682s)
3122 return -ENOMEM;
3123
3124 i2c_set_clientdata(client: i2c, data: rt5682s);
3125
3126 rt5682s->pdata = i2s_default_platform_data;
3127
3128 if (pdata)
3129 rt5682s->pdata = *pdata;
3130 else
3131 rt5682s_parse_dt(rt5682s, dev: &i2c->dev);
3132
3133 rt5682s->regmap = devm_regmap_init_i2c(i2c, &rt5682s_regmap);
3134 if (IS_ERR(ptr: rt5682s->regmap)) {
3135 ret = PTR_ERR(ptr: rt5682s->regmap);
3136 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", ret);
3137 return ret;
3138 }
3139
3140 for (i = 0; i < ARRAY_SIZE(rt5682s->supplies); i++)
3141 rt5682s->supplies[i].supply = rt5682s_supply_names[i];
3142
3143 ret = devm_regulator_bulk_get(dev: &i2c->dev,
3144 ARRAY_SIZE(rt5682s->supplies), consumers: rt5682s->supplies);
3145 if (ret) {
3146 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3147 return ret;
3148 }
3149
3150 ret = devm_add_action_or_reset(&i2c->dev, rt5682s_i2c_disable_regulators, rt5682s);
3151 if (ret)
3152 return ret;
3153
3154 ret = regulator_enable(regulator: rt5682s->supplies[RT5682S_SUPPLY_MICVDD].consumer);
3155 if (ret) {
3156 dev_err(&i2c->dev, "Failed to enable supply MICVDD: %d\n", ret);
3157 return ret;
3158 }
3159 usleep_range(min: 1000, max: 1500);
3160
3161 ret = regulator_enable(regulator: rt5682s->supplies[RT5682S_SUPPLY_AVDD].consumer);
3162 if (ret) {
3163 dev_err(&i2c->dev, "Failed to enable supply AVDD: %d\n", ret);
3164 return ret;
3165 }
3166
3167 ret = regulator_enable(regulator: rt5682s->supplies[RT5682S_SUPPLY_DBVDD].consumer);
3168 if (ret) {
3169 dev_err(&i2c->dev, "Failed to enable supply DBVDD: %d\n", ret);
3170 return ret;
3171 }
3172
3173 ret = regulator_enable(regulator: rt5682s->supplies[RT5682S_SUPPLY_LDO1_IN].consumer);
3174 if (ret) {
3175 dev_err(&i2c->dev, "Failed to enable supply LDO1-IN: %d\n", ret);
3176 return ret;
3177 }
3178
3179 rt5682s->ldo1_en = devm_gpiod_get_optional(dev: &i2c->dev,
3180 con_id: "realtek,ldo1-en",
3181 flags: GPIOD_OUT_HIGH);
3182 if (IS_ERR(ptr: rt5682s->ldo1_en)) {
3183 dev_err(&i2c->dev, "Fail gpio request ldo1_en\n");
3184 return PTR_ERR(ptr: rt5682s->ldo1_en);
3185 }
3186
3187 /* Sleep for 50 ms minimum */
3188 usleep_range(min: 50000, max: 55000);
3189
3190 regmap_read(map: rt5682s->regmap, RT5682S_DEVICE_ID, val: &val);
3191 if (val != DEVICE_ID) {
3192 dev_err(&i2c->dev, "Device with ID register %x is not rt5682s\n", val);
3193 return -ENODEV;
3194 }
3195
3196 rt5682s_reset(rt5682s);
3197 rt5682s_apply_patch_list(rt5682s, dev: &i2c->dev);
3198
3199 regmap_update_bits(map: rt5682s->regmap, RT5682S_PWR_DIG_2,
3200 RT5682S_DLDO_I_LIMIT_MASK, RT5682S_DLDO_I_LIMIT_DIS);
3201 usleep_range(min: 20000, max: 25000);
3202
3203 mutex_init(&rt5682s->calibrate_mutex);
3204 mutex_init(&rt5682s->sar_mutex);
3205 mutex_init(&rt5682s->wclk_mutex);
3206 rt5682s_calibrate(rt5682s);
3207
3208 regmap_update_bits(map: rt5682s->regmap, RT5682S_MICBIAS_2,
3209 RT5682S_PWR_CLK25M_MASK | RT5682S_PWR_CLK1M_MASK,
3210 RT5682S_PWR_CLK25M_PD | RT5682S_PWR_CLK1M_PU);
3211 regmap_update_bits(map: rt5682s->regmap, RT5682S_PWR_ANLG_1,
3212 RT5682S_PWR_BG, RT5682S_PWR_BG);
3213 regmap_update_bits(map: rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2,
3214 RT5682S_HP_SIG_SRC_MASK, RT5682S_HP_SIG_SRC_1BIT_CTL);
3215 regmap_update_bits(map: rt5682s->regmap, RT5682S_HP_CHARGE_PUMP_2,
3216 RT5682S_PM_HP_MASK, RT5682S_PM_HP_HV);
3217 regmap_update_bits(map: rt5682s->regmap, RT5682S_HP_AMP_DET_CTL_1,
3218 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M);
3219
3220 /* DMIC data pin */
3221 switch (rt5682s->pdata.dmic1_data_pin) {
3222 case RT5682S_DMIC1_DATA_NULL:
3223 break;
3224 case RT5682S_DMIC1_DATA_GPIO2: /* share with LRCK2 */
3225 regmap_update_bits(map: rt5682s->regmap, RT5682S_DMIC_CTRL_1,
3226 RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO2);
3227 regmap_update_bits(map: rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3228 RT5682S_GP2_PIN_MASK, RT5682S_GP2_PIN_DMIC_SDA);
3229 break;
3230 case RT5682S_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
3231 regmap_update_bits(map: rt5682s->regmap, RT5682S_DMIC_CTRL_1,
3232 RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO5);
3233 regmap_update_bits(map: rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3234 RT5682S_GP5_PIN_MASK, RT5682S_GP5_PIN_DMIC_SDA);
3235 break;
3236 default:
3237 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
3238 break;
3239 }
3240
3241 /* DMIC clk pin */
3242 switch (rt5682s->pdata.dmic1_clk_pin) {
3243 case RT5682S_DMIC1_CLK_NULL:
3244 break;
3245 case RT5682S_DMIC1_CLK_GPIO1: /* share with IRQ */
3246 regmap_update_bits(map: rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3247 RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_DMIC_CLK);
3248 break;
3249 case RT5682S_DMIC1_CLK_GPIO3: /* share with BCLK2 */
3250 regmap_update_bits(map: rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3251 RT5682S_GP3_PIN_MASK, RT5682S_GP3_PIN_DMIC_CLK);
3252 if (rt5682s->pdata.dmic_clk_driving_high)
3253 regmap_update_bits(map: rt5682s->regmap, RT5682S_PAD_DRIVING_CTRL,
3254 RT5682S_PAD_DRV_GP3_MASK, RT5682S_PAD_DRV_GP3_HIGH);
3255 break;
3256 default:
3257 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
3258 break;
3259 }
3260
3261 /* LDO output voltage control */
3262 switch (rt5682s->pdata.ldo_dacref) {
3263 case RT5682S_LDO_1_607V:
3264 break;
3265 case RT5682S_LDO_1_5V:
3266 regmap_update_bits(map: rt5682s->regmap, RT5682S_BIAS_CUR_CTRL_7,
3267 RT5682S_LDO_DACREF_MASK, RT5682S_LDO_DACREF_1_5V);
3268 break;
3269 case RT5682S_LDO_1_406V:
3270 regmap_update_bits(map: rt5682s->regmap, RT5682S_BIAS_CUR_CTRL_7,
3271 RT5682S_LDO_DACREF_MASK, RT5682S_LDO_DACREF_1_406V);
3272 break;
3273 case RT5682S_LDO_1_731V:
3274 regmap_update_bits(map: rt5682s->regmap, RT5682S_BIAS_CUR_CTRL_7,
3275 RT5682S_LDO_DACREF_MASK, RT5682S_LDO_DACREF_1_731V);
3276 break;
3277 default:
3278 dev_warn(&i2c->dev, "invalid LDO output setting.\n");
3279 break;
3280 }
3281
3282 INIT_DELAYED_WORK(&rt5682s->jack_detect_work, rt5682s_jack_detect_handler);
3283 INIT_DELAYED_WORK(&rt5682s->jd_check_work, rt5682s_jd_check_handler);
3284
3285 if (i2c->irq) {
3286 ret = devm_request_threaded_irq(dev: &i2c->dev, irq: i2c->irq, NULL, thread_fn: rt5682s_irq,
3287 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
3288 devname: "rt5682s", dev_id: rt5682s);
3289 if (!ret)
3290 rt5682s->irq = i2c->irq;
3291 else
3292 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);
3293 }
3294
3295 return devm_snd_soc_register_component(dev: &i2c->dev, component_driver: &rt5682s_soc_component_dev,
3296 dai_drv: rt5682s_dai, ARRAY_SIZE(rt5682s_dai));
3297}
3298
3299static void rt5682s_i2c_shutdown(struct i2c_client *client)
3300{
3301 struct rt5682s_priv *rt5682s = i2c_get_clientdata(client);
3302
3303 disable_irq(irq: client->irq);
3304 cancel_delayed_work_sync(dwork: &rt5682s->jack_detect_work);
3305 cancel_delayed_work_sync(dwork: &rt5682s->jd_check_work);
3306
3307 rt5682s_reset(rt5682s);
3308}
3309
3310static void rt5682s_i2c_remove(struct i2c_client *client)
3311{
3312 rt5682s_i2c_shutdown(client);
3313}
3314
3315static const struct of_device_id rt5682s_of_match[] = {
3316 {.compatible = "realtek,rt5682s"},
3317 {},
3318};
3319MODULE_DEVICE_TABLE(of, rt5682s_of_match);
3320
3321static const struct acpi_device_id rt5682s_acpi_match[] = {
3322 {"RTL5682", 0,},
3323 {},
3324};
3325MODULE_DEVICE_TABLE(acpi, rt5682s_acpi_match);
3326
3327static const struct i2c_device_id rt5682s_i2c_id[] = {
3328 {"rt5682s"},
3329 {}
3330};
3331MODULE_DEVICE_TABLE(i2c, rt5682s_i2c_id);
3332
3333static struct i2c_driver rt5682s_i2c_driver = {
3334 .driver = {
3335 .name = "rt5682s",
3336 .of_match_table = rt5682s_of_match,
3337 .acpi_match_table = rt5682s_acpi_match,
3338 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3339 },
3340 .probe = rt5682s_i2c_probe,
3341 .remove = rt5682s_i2c_remove,
3342 .shutdown = rt5682s_i2c_shutdown,
3343 .id_table = rt5682s_i2c_id,
3344};
3345module_i2c_driver(rt5682s_i2c_driver);
3346
3347MODULE_DESCRIPTION("ASoC RT5682I-VS driver");
3348MODULE_AUTHOR("Derek Fang <derek.fang@realtek.com>");
3349MODULE_LICENSE("GPL v2");
3350

source code of linux/sound/soc/codecs/rt5682s.c