1	// SPDX-License-Identifier: GPL-2.0-or-later
2	/*
3	* ALSA driver for RME Digi9652 audio interfaces
4	*
5	* Copyright (c) 1999 IEM - Winfried Ritsch
6	* Copyright (c) 1999-2001 Paul Davis
7	*/
8
9	#include <linux/delay.h>
10	#include <linux/init.h>
11	#include <linux/interrupt.h>
12	#include <linux/pci.h>
13	#include <linux/module.h>
14	#include <linux/io.h>
15	#include <linux/nospec.h>
16
17	#include <sound/core.h>
18	#include <sound/control.h>
19	#include <sound/pcm.h>
20	#include <sound/info.h>
21	#include <sound/asoundef.h>
22	#include <sound/initval.h>
23
24	#include <asm/current.h>
25
26	static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
27	static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
28	static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
29	static bool precise_ptr[SNDRV_CARDS]; /* Enable precise pointer */
30
31	module_param_array(index, int, NULL, 0444);
32	MODULE_PARM_DESC(index, "Index value for RME Digi9652 (Hammerfall) soundcard.");
33	module_param_array(id, charp, NULL, 0444);
34	MODULE_PARM_DESC(id, "ID string for RME Digi9652 (Hammerfall) soundcard.");
35	module_param_array(enable, bool, NULL, 0444);
36	MODULE_PARM_DESC(enable, "Enable/disable specific RME96{52,36} soundcards.");
37	module_param_array(precise_ptr, bool, NULL, 0444);
38	MODULE_PARM_DESC(precise_ptr, "Enable precise pointer (doesn't work reliably).");
39	MODULE_AUTHOR("Paul Davis <pbd@op.net>, Winfried Ritsch");
40	MODULE_DESCRIPTION("RME Digi9652/Digi9636");
41	MODULE_LICENSE("GPL");
42
43	/* The Hammerfall has two sets of 24 ADAT + 2 S/PDIF channels, one for
44	capture, one for playback. Both the ADAT and S/PDIF channels appear
45	to the host CPU in the same block of memory. There is no functional
46	difference between them in terms of access.
47
48	The Hammerfall Light is identical to the Hammerfall, except that it
49	has 2 sets 18 channels (16 ADAT + 2 S/PDIF) for capture and playback.
50	*/
51
52	#define RME9652_NCHANNELS 26
53	#define RME9636_NCHANNELS 18
54
55	/* Preferred sync source choices - used by "sync_pref" control switch */
56
57	#define RME9652_SYNC_FROM_SPDIF 0
58	#define RME9652_SYNC_FROM_ADAT1 1
59	#define RME9652_SYNC_FROM_ADAT2 2
60	#define RME9652_SYNC_FROM_ADAT3 3
61
62	/* Possible sources of S/PDIF input */
63
64	#define RME9652_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
65	#define RME9652_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
66	#define RME9652_SPDIFIN_INTERN 2 /* internal (CDROM) */
67
68	/* ------------- Status-Register bits --------------------- */
69
70	#define RME9652_IRQ (1<<0) /* IRQ is High if not reset by irq_clear */
71	#define RME9652_lock_2 (1<<1) /* ADAT 3-PLL: 1=locked, 0=unlocked */
72	#define RME9652_lock_1 (1<<2) /* ADAT 2-PLL: 1=locked, 0=unlocked */
73	#define RME9652_lock_0 (1<<3) /* ADAT 1-PLL: 1=locked, 0=unlocked */
74	#define RME9652_fs48 (1<<4) /* sample rate is 0=44.1/88.2,1=48/96 Khz */
75	#define RME9652_wsel_rd (1<<5) /* if Word-Clock is used and valid then 1 */
76	/* bits 6-15 encode h/w buffer pointer position */
77	#define RME9652_sync_2 (1<<16) /* if ADAT-IN 3 in sync to system clock */
78	#define RME9652_sync_1 (1<<17) /* if ADAT-IN 2 in sync to system clock */
79	#define RME9652_sync_0 (1<<18) /* if ADAT-IN 1 in sync to system clock */
80	#define RME9652_DS_rd (1<<19) /* 1=Double Speed Mode, 0=Normal Speed */
81	#define RME9652_tc_busy (1<<20) /* 1=time-code copy in progress (960ms) */
82	#define RME9652_tc_out (1<<21) /* time-code out bit */
83	#define RME9652_F_0 (1<<22) /* 000=64kHz, 100=88.2kHz, 011=96kHz */
84	#define RME9652_F_1 (1<<23) /* 111=32kHz, 110=44.1kHz, 101=48kHz, */
85	#define RME9652_F_2 (1<<24) /* external Crystal Chip if ERF=1 */
86	#define RME9652_ERF (1<<25) /* Error-Flag of SDPIF Receiver (1=No Lock) */
87	#define RME9652_buffer_id (1<<26) /* toggles by each interrupt on rec/play */
88	#define RME9652_tc_valid (1<<27) /* 1 = a signal is detected on time-code input */
89	#define RME9652_SPDIF_READ (1<<28) /* byte available from Rev 1.5+ S/PDIF interface */
90
91	#define RME9652_sync (RME9652_sync_0|RME9652_sync_1|RME9652_sync_2)
92	#define RME9652_lock (RME9652_lock_0|RME9652_lock_1|RME9652_lock_2)
93	#define RME9652_F (RME9652_F_0|RME9652_F_1|RME9652_F_2)
94	#define rme9652_decode_spdif_rate(x) ((x)>>22)
95
96	/* Bit 6..15 : h/w buffer pointer */
97
98	#define RME9652_buf_pos 0x000FFC0
99
100	/* Bits 31,30,29 are bits 5,4,3 of h/w pointer position on later
101	Rev G EEPROMS and Rev 1.5 cards or later.
102	*/
103
104	#define RME9652_REV15_buf_pos(x) ((((x)&0xE0000000)>>26)|((x)&RME9652_buf_pos))
105
106	/* amount of io space we remap for register access. i'm not sure we
107	even need this much, but 1K is nice round number :)
108	*/
109
110	#define RME9652_IO_EXTENT 1024
111
112	#define RME9652_init_buffer 0
113	#define RME9652_play_buffer 32 /* holds ptr to 26x64kBit host RAM */
114	#define RME9652_rec_buffer 36 /* holds ptr to 26x64kBit host RAM */
115	#define RME9652_control_register 64
116	#define RME9652_irq_clear 96
117	#define RME9652_time_code 100 /* useful if used with alesis adat */
118	#define RME9652_thru_base 128 /* 132...228 Thru for 26 channels */
119
120	/* Read-only registers */
121
122	/* Writing to any of the register locations writes to the status
123	register. We'll use the first location as our point of access.
124	*/
125
126	#define RME9652_status_register 0
127
128	/* --------- Control-Register Bits ---------------- */
129
130
131	#define RME9652_start_bit (1<<0) /* start record/play */
132	/* bits 1-3 encode buffersize/latency */
133	#define RME9652_Master (1<<4) /* Clock Mode Master=1,Slave/Auto=0 */
134	#define RME9652_IE (1<<5) /* Interrupt Enable */
135	#define RME9652_freq (1<<6) /* samplerate 0=44.1/88.2, 1=48/96 kHz */
136	#define RME9652_freq1 (1<<7) /* if 0, 32kHz, else always 1 */
137	#define RME9652_DS (1<<8) /* Doule Speed 0=44.1/48, 1=88.2/96 Khz */
138	#define RME9652_PRO (1<<9) /* S/PDIF out: 0=consumer, 1=professional */
139	#define RME9652_EMP (1<<10) /* Emphasis 0=None, 1=ON */
140	#define RME9652_Dolby (1<<11) /* Non-audio bit 1=set, 0=unset */
141	#define RME9652_opt_out (1<<12) /* Use 1st optical OUT as SPDIF: 1=yes,0=no */
142	#define RME9652_wsel (1<<13) /* use Wordclock as sync (overwrites master) */
143	#define RME9652_inp_0 (1<<14) /* SPDIF-IN: 00=optical (ADAT1), */
144	#define RME9652_inp_1 (1<<15) /* 01=koaxial (Cinch), 10=Internal CDROM */
145	#define RME9652_SyncPref_ADAT2 (1<<16)
146	#define RME9652_SyncPref_ADAT3 (1<<17)
147	#define RME9652_SPDIF_RESET (1<<18) /* Rev 1.5+: h/w S/PDIF receiver */
148	#define RME9652_SPDIF_SELECT (1<<19)
149	#define RME9652_SPDIF_CLOCK (1<<20)
150	#define RME9652_SPDIF_WRITE (1<<21)
151	#define RME9652_ADAT1_INTERNAL (1<<22) /* Rev 1.5+: if set, internal CD connector carries ADAT */
152
153	/* buffersize = 512Bytes * 2^n, where n is made from Bit2 ... Bit0 */
154
155	#define RME9652_latency 0x0e
156	#define rme9652_encode_latency(x) (((x)&0x7)<<1)
157	#define rme9652_decode_latency(x) (((x)>>1)&0x7)
158	#define rme9652_running_double_speed(s) ((s)->control_register & RME9652_DS)
159	#define RME9652_inp (RME9652_inp_0|RME9652_inp_1)
160	#define rme9652_encode_spdif_in(x) (((x)&0x3)<<14)
161	#define rme9652_decode_spdif_in(x) (((x)>>14)&0x3)
162
163	#define RME9652_SyncPref_Mask (RME9652_SyncPref_ADAT2|RME9652_SyncPref_ADAT3)
164	#define RME9652_SyncPref_ADAT1 0
165	#define RME9652_SyncPref_SPDIF (RME9652_SyncPref_ADAT2|RME9652_SyncPref_ADAT3)
166
167	/* the size of a substream (1 mono data stream) */
168
169	#define RME9652_CHANNEL_BUFFER_SAMPLES (16*1024)
170	#define RME9652_CHANNEL_BUFFER_BYTES (4*RME9652_CHANNEL_BUFFER_SAMPLES)
171
172	/* the size of the area we need to allocate for DMA transfers. the
173	size is the same regardless of the number of channels - the
174	9636 still uses the same memory area.
175
176	Note that we allocate 1 more channel than is apparently needed
177	because the h/w seems to write 1 byte beyond the end of the last
178	page. Sigh.
179	*/
180
181	#define RME9652_DMA_AREA_BYTES ((RME9652_NCHANNELS+1) * RME9652_CHANNEL_BUFFER_BYTES)
182	#define RME9652_DMA_AREA_KILOBYTES (RME9652_DMA_AREA_BYTES/1024)
183
184	struct snd_rme9652 {
185	int dev;
186
187	spinlock_t lock;
188	int irq;
189	unsigned long port;
190	void __iomem *iobase;
191
192	int precise_ptr;
193
194	u32 control_register; /* cached value */
195	u32 thru_bits; /* thru 1=on, 0=off channel 1=Bit1... channel 26= Bit26 */
196
197	u32 creg_spdif;
198	u32 creg_spdif_stream;
199
200	char *card_name; /* hammerfall or hammerfall light names */
201
202	size_t hw_offsetmask; /* &-with status register to get real hw_offset */
203	size_t prev_hw_offset; /* previous hw offset */
204	size_t max_jitter; /* maximum jitter in frames for
205	hw pointer */
206	size_t period_bytes; /* guess what this is */
207
208	unsigned char ds_channels;
209	unsigned char ss_channels; /* different for hammerfall/hammerfall-light */
210
211	/* DMA buffers; those are copied instances from the original snd_dma_buf
212	* objects (which are managed via devres) for the address alignments
213	*/
214	struct snd_dma_buffer playback_dma_buf;
215	struct snd_dma_buffer capture_dma_buf;
216
217	unsigned char *capture_buffer; /* suitably aligned address */
218	unsigned char *playback_buffer; /* suitably aligned address */
219
220	pid_t capture_pid;
221	pid_t playback_pid;
222
223	struct snd_pcm_substream *capture_substream;
224	struct snd_pcm_substream *playback_substream;
225	int running;
226
227	int passthru; /* non-zero if doing pass-thru */
228	int hw_rev; /* h/w rev * 10 (i.e. 1.5 has hw_rev = 15) */
229
230	int last_spdif_sample_rate; /* so that we can catch externally ... */
231	int last_adat_sample_rate; /* ... induced rate changes */
232
233	const signed char *channel_map;
234
235	struct snd_card *card;
236	struct snd_pcm *pcm;
237	struct pci_dev *pci;
238	struct snd_kcontrol *spdif_ctl;
239
240	};
241
242	/* These tables map the ALSA channels 1..N to the channels that we
243	need to use in order to find the relevant channel buffer. RME
244	refer to this kind of mapping as between "the ADAT channel and
245	the DMA channel." We index it using the logical audio channel,
246	and the value is the DMA channel (i.e. channel buffer number)
247	where the data for that channel can be read/written from/to.
248	*/
249
250	static const signed char channel_map_9652_ss[26] = {
251	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
252	18, 19, 20, 21, 22, 23, 24, 25
253	};
254
255	static const signed char channel_map_9636_ss[26] = {
256	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
257	/* channels 16 and 17 are S/PDIF */
258	24, 25,
259	/* channels 18-25 don't exist */
260	-1, -1, -1, -1, -1, -1, -1, -1
261	};
262
263	static const signed char channel_map_9652_ds[26] = {
264	/* ADAT channels are remapped */
265	1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
266	/* channels 12 and 13 are S/PDIF */
267	24, 25,
268	/* others don't exist */
269	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
270	};
271
272	static const signed char channel_map_9636_ds[26] = {
273	/* ADAT channels are remapped */
274	1, 3, 5, 7, 9, 11, 13, 15,
275	/* channels 8 and 9 are S/PDIF */
276	24, 25,
277	/* others don't exist */
278	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
279	};
280
281	static struct snd_dma_buffer *
282	snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size)
283	{
284	return snd_devm_alloc_pages(dev: &pci->dev, SNDRV_DMA_TYPE_DEV, size);
285	}
286
287	static const struct pci_device_id snd_rme9652_ids[] = {
288	{
289	.vendor = 0x10ee,
290	.device = 0x3fc4,
291	.subvendor = PCI_ANY_ID,
292	.subdevice = PCI_ANY_ID,
293	}, /* RME Digi9652 */
294	{ 0, },
295	};
296
297	MODULE_DEVICE_TABLE(pci, snd_rme9652_ids);
298
299	static inline void rme9652_write(struct snd_rme9652 *rme9652, int reg, int val)
300	{
301	writel(val, addr: rme9652->iobase + reg);
302	}
303
304	static inline unsigned int rme9652_read(struct snd_rme9652 *rme9652, int reg)
305	{
306	return readl(addr: rme9652->iobase + reg);
307	}
308
309	static inline int snd_rme9652_use_is_exclusive(struct snd_rme9652 *rme9652)
310	{
311	guard(spinlock_irqsave)(l: &rme9652->lock);
312	if ((rme9652->playback_pid != rme9652->capture_pid) &&
313	(rme9652->playback_pid >= 0) && (rme9652->capture_pid >= 0))
314	return 0;
315	return 1;
316	}
317
318	static inline int rme9652_adat_sample_rate(struct snd_rme9652 *rme9652)
319	{
320	if (rme9652_running_double_speed(rme9652)) {
321	return (rme9652_read(rme9652, RME9652_status_register) &
322	RME9652_fs48) ? 96000 : 88200;
323	} else {
324	return (rme9652_read(rme9652, RME9652_status_register) &
325	RME9652_fs48) ? 48000 : 44100;
326	}
327	}
328
329	static inline void rme9652_compute_period_size(struct snd_rme9652 *rme9652)
330	{
331	unsigned int i;
332
333	i = rme9652->control_register & RME9652_latency;
334	rme9652->period_bytes = 1 << ((rme9652_decode_latency(i) + 8));
335	rme9652->hw_offsetmask =
336	(rme9652->period_bytes * 2 - 1) & RME9652_buf_pos;
337	rme9652->max_jitter = 80;
338	}
339
340	static snd_pcm_uframes_t rme9652_hw_pointer(struct snd_rme9652 *rme9652)
341	{
342	int status;
343	unsigned int offset, frag;
344	snd_pcm_uframes_t period_size = rme9652->period_bytes / 4;
345	snd_pcm_sframes_t delta;
346
347	status = rme9652_read(rme9652, RME9652_status_register);
348	if (!rme9652->precise_ptr)
349	return (status & RME9652_buffer_id) ? period_size : 0;
350	offset = status & RME9652_buf_pos;
351
352	/* The hardware may give a backward movement for up to 80 frames
353	Martin Kirst <martin.kirst@freenet.de> knows the details.
354	*/
355
356	delta = rme9652->prev_hw_offset - offset;
357	delta &= 0xffff;
358	if (delta <= (snd_pcm_sframes_t)rme9652->max_jitter * 4)
359	offset = rme9652->prev_hw_offset;
360	else
361	rme9652->prev_hw_offset = offset;
362	offset &= rme9652->hw_offsetmask;
363	offset /= 4;
364	frag = status & RME9652_buffer_id;
365
366	if (offset < period_size) {
367	if (offset > rme9652->max_jitter) {
368	if (frag)
369	dev_err(rme9652->card->dev,
370	"Unexpected hw_pointer position (bufid == 0): status: %x offset: %d\n",
371	status, offset);
372	} else if (!frag)
373	return 0;
374	offset -= rme9652->max_jitter;
375	if ((int)offset < 0)
376	offset += period_size * 2;
377	} else {
378	if (offset > period_size + rme9652->max_jitter) {
379	if (!frag)
380	dev_err(rme9652->card->dev,
381	"Unexpected hw_pointer position (bufid == 1): status: %x offset: %d\n",
382	status, offset);
383	} else if (frag)
384	return period_size;
385	offset -= rme9652->max_jitter;
386	}
387
388	return offset;
389	}
390
391	static inline void rme9652_reset_hw_pointer(struct snd_rme9652 *rme9652)
392	{
393	int i;
394
395	/* reset the FIFO pointer to zero. We do this by writing to 8
396	registers, each of which is a 32bit wide register, and set
397	them all to zero. Note that s->iobase is a pointer to
398	int32, not pointer to char.
399	*/
400
401	for (i = 0; i < 8; i++) {
402	rme9652_write(rme9652, reg: i * 4, val: 0);
403	udelay(usec: 10);
404	}
405	rme9652->prev_hw_offset = 0;
406	}
407
408	static inline void rme9652_start(struct snd_rme9652 *s)
409	{
410	s->control_register |= (RME9652_IE | RME9652_start_bit);
411	rme9652_write(rme9652: s, RME9652_control_register, val: s->control_register);
412	}
413
414	static inline void rme9652_stop(struct snd_rme9652 *s)
415	{
416	s->control_register &= ~(RME9652_start_bit | RME9652_IE);
417	rme9652_write(rme9652: s, RME9652_control_register, val: s->control_register);
418	}
419
420	static int rme9652_set_interrupt_interval(struct snd_rme9652 *s,
421	unsigned int frames)
422	{
423	int restart = 0;
424	int n;
425
426	guard(spinlock_irq)(l: &s->lock);
427
428	restart = s->running;
429	if (restart)
430	rme9652_stop(s);
431
432	frames >>= 7;
433	n = 0;
434	while (frames) {
435	n++;
436	frames >>= 1;
437	}
438
439	s->control_register &= ~RME9652_latency;
440	s->control_register |= rme9652_encode_latency(n);
441
442	rme9652_write(rme9652: s, RME9652_control_register, val: s->control_register);
443
444	rme9652_compute_period_size(rme9652: s);
445
446	if (restart)
447	rme9652_start(s);
448
449	return 0;
450	}
451
452	static int rme9652_set_rate(struct snd_rme9652 *rme9652, int rate)
453	{
454	int restart;
455	int reject_if_open = 0;
456	int xrate;
457
458	if (!snd_rme9652_use_is_exclusive (rme9652)) {
459	return -EBUSY;
460	}
461
462	/* Changing from a "single speed" to a "double speed" rate is
463	not allowed if any substreams are open. This is because
464	such a change causes a shift in the location of
465	the DMA buffers and a reduction in the number of available
466	buffers.
467
468	Note that a similar but essentially insoluble problem
469	exists for externally-driven rate changes. All we can do
470	is to flag rate changes in the read/write routines.
471	*/
472
473	guard(spinlock_irq)(l: &rme9652->lock);
474	xrate = rme9652_adat_sample_rate(rme9652);
475
476	switch (rate) {
477	case 44100:
478	if (xrate > 48000) {
479	reject_if_open = 1;
480	}
481	rate = 0;
482	break;
483	case 48000:
484	if (xrate > 48000) {
485	reject_if_open = 1;
486	}
487	rate = RME9652_freq;
488	break;
489	case 88200:
490	if (xrate < 48000) {
491	reject_if_open = 1;
492	}
493	rate = RME9652_DS;
494	break;
495	case 96000:
496	if (xrate < 48000) {
497	reject_if_open = 1;
498	}
499	rate = RME9652_DS | RME9652_freq;
500	break;
501	default:
502	return -EINVAL;
503	}
504
505	if (reject_if_open && (rme9652->capture_pid >= 0 || rme9652->playback_pid >= 0))
506	return -EBUSY;
507
508	restart = rme9652->running;
509	if (restart)
510	rme9652_stop(s: rme9652);
511	rme9652->control_register &= ~(RME9652_freq | RME9652_DS);
512	rme9652->control_register |= rate;
513	rme9652_write(rme9652, RME9652_control_register, val: rme9652->control_register);
514
515	if (restart)
516	rme9652_start(s: rme9652);
517
518	if (rate & RME9652_DS) {
519	if (rme9652->ss_channels == RME9652_NCHANNELS) {
520	rme9652->channel_map = channel_map_9652_ds;
521	} else {
522	rme9652->channel_map = channel_map_9636_ds;
523	}
524	} else {
525	if (rme9652->ss_channels == RME9652_NCHANNELS) {
526	rme9652->channel_map = channel_map_9652_ss;
527	} else {
528	rme9652->channel_map = channel_map_9636_ss;
529	}
530	}
531
532	return 0;
533	}
534
535	static void rme9652_set_thru(struct snd_rme9652 *rme9652, int channel, int enable)
536	{
537	int i;
538
539	rme9652->passthru = 0;
540
541	if (channel < 0) {
542
543	/* set thru for all channels */
544
545	if (enable) {
546	for (i = 0; i < RME9652_NCHANNELS; i++) {
547	rme9652->thru_bits |= (1 << i);
548	rme9652_write(rme9652, RME9652_thru_base + i * 4, val: 1);
549	}
550	} else {
551	for (i = 0; i < RME9652_NCHANNELS; i++) {
552	rme9652->thru_bits &= ~(1 << i);
553	rme9652_write(rme9652, RME9652_thru_base + i * 4, val: 0);
554	}
555	}
556
557	} else {
558	int mapped_channel;
559
560	mapped_channel = rme9652->channel_map[channel];
561
562	if (enable) {
563	rme9652->thru_bits |= (1 << mapped_channel);
564	} else {
565	rme9652->thru_bits &= ~(1 << mapped_channel);
566	}
567
568	rme9652_write(rme9652,
569	RME9652_thru_base + mapped_channel * 4,
570	val: enable ? 1 : 0);
571	}
572	}
573
574	static int rme9652_set_passthru(struct snd_rme9652 *rme9652, int onoff)
575	{
576	if (onoff) {
577	rme9652_set_thru(rme9652, channel: -1, enable: 1);
578
579	/* we don't want interrupts, so do a
580	custom version of rme9652_start().
581	*/
582
583	rme9652->control_register =
584	RME9652_inp_0 |
585	rme9652_encode_latency(7) |
586	RME9652_start_bit;
587
588	rme9652_reset_hw_pointer(rme9652);
589
590	rme9652_write(rme9652, RME9652_control_register,
591	val: rme9652->control_register);
592	rme9652->passthru = 1;
593	} else {
594	rme9652_set_thru(rme9652, channel: -1, enable: 0);
595	rme9652_stop(s: rme9652);
596	rme9652->passthru = 0;
597	}
598
599	return 0;
600	}
601
602	static void rme9652_spdif_set_bit (struct snd_rme9652 *rme9652, int mask, int onoff)
603	{
604	if (onoff)
605	rme9652->control_register |= mask;
606	else
607	rme9652->control_register &= ~mask;
608
609	rme9652_write(rme9652, RME9652_control_register, val: rme9652->control_register);
610	}
611
612	static void rme9652_spdif_write_byte (struct snd_rme9652 *rme9652, const int val)
613	{
614	long mask;
615	long i;
616
617	for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) {
618	if (val & mask)
619	rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_WRITE, onoff: 1);
620	else
621	rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_WRITE, onoff: 0);
622
623	rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, onoff: 1);
624	rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, onoff: 0);
625	}
626	}
627
628	static int rme9652_spdif_read_byte (struct snd_rme9652 *rme9652)
629	{
630	long mask;
631	long val;
632	long i;
633
634	val = 0;
635
636	for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) {
637	rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, onoff: 1);
638	if (rme9652_read (rme9652, RME9652_status_register) & RME9652_SPDIF_READ)
639	val |= mask;
640	rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, onoff: 0);
641	}
642
643	return val;
644	}
645
646	static void rme9652_write_spdif_codec (struct snd_rme9652 *rme9652, const int address, const int data)
647	{
648	rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, onoff: 1);
649	rme9652_spdif_write_byte (rme9652, val: 0x20);
650	rme9652_spdif_write_byte (rme9652, val: address);
651	rme9652_spdif_write_byte (rme9652, val: data);
652	rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, onoff: 0);
653	}
654
655
656	static int rme9652_spdif_read_codec (struct snd_rme9652 *rme9652, const int address)
657	{
658	int ret;
659
660	rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, onoff: 1);
661	rme9652_spdif_write_byte (rme9652, val: 0x20);
662	rme9652_spdif_write_byte (rme9652, val: address);
663	rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, onoff: 0);
664	rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, onoff: 1);
665
666	rme9652_spdif_write_byte (rme9652, val: 0x21);
667	ret = rme9652_spdif_read_byte (rme9652);
668	rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, onoff: 0);
669
670	return ret;
671	}
672
673	static void rme9652_initialize_spdif_receiver (struct snd_rme9652 *rme9652)
674	{
675	/* XXX what unsets this ? */
676
677	rme9652->control_register |= RME9652_SPDIF_RESET;
678
679	rme9652_write_spdif_codec (rme9652, address: 4, data: 0x40);
680	rme9652_write_spdif_codec (rme9652, address: 17, data: 0x13);
681	rme9652_write_spdif_codec (rme9652, address: 6, data: 0x02);
682	}
683
684	static inline int rme9652_spdif_sample_rate(struct snd_rme9652 *s)
685	{
686	unsigned int rate_bits;
687
688	if (rme9652_read(rme9652: s, RME9652_status_register) & RME9652_ERF) {
689	return -1; /* error condition */
690	}
691
692	if (s->hw_rev == 15) {
693
694	int x, y, ret;
695
696	x = rme9652_spdif_read_codec (rme9652: s, address: 30);
697
698	if (x != 0)
699	y = 48000 * 64 / x;
700	else
701	y = 0;
702
703	if (y > 30400 && y < 33600) ret = 32000;
704	else if (y > 41900 && y < 46000) ret = 44100;
705	else if (y > 46000 && y < 50400) ret = 48000;
706	else if (y > 60800 && y < 67200) ret = 64000;
707	else if (y > 83700 && y < 92000) ret = 88200;
708	else if (y > 92000 && y < 100000) ret = 96000;
709	else ret = 0;
710	return ret;
711	}
712
713	rate_bits = rme9652_read(rme9652: s, RME9652_status_register) & RME9652_F;
714
715	switch (rme9652_decode_spdif_rate(rate_bits)) {
716	case 0x7:
717	return 32000;
718
719	case 0x6:
720	return 44100;
721
722	case 0x5:
723	return 48000;
724
725	case 0x4:
726	return 88200;
727
728	case 0x3:
729	return 96000;
730
731	case 0x0:
732	return 64000;
733
734	default:
735	dev_err(s->card->dev,
736	"%s: unknown S/PDIF input rate (bits = 0x%x)\n",
737	s->card_name, rate_bits);
738	return 0;
739	}
740	}
741
742	/*-----------------------------------------------------------------------------
743	Control Interface
744	----------------------------------------------------------------------------*/
745
746	static u32 snd_rme9652_convert_from_aes(struct snd_aes_iec958 *aes)
747	{
748	u32 val = 0;
749	val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME9652_PRO : 0;
750	val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME9652_Dolby : 0;
751	if (val & RME9652_PRO)
752	val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME9652_EMP : 0;
753	else
754	val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME9652_EMP : 0;
755	return val;
756	}
757
758	static void snd_rme9652_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
759	{
760	aes->status[0] = ((val & RME9652_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
761	((val & RME9652_Dolby) ? IEC958_AES0_NONAUDIO : 0);
762	if (val & RME9652_PRO)
763	aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
764	else
765	aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
766	}
767
768	static int snd_rme9652_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
769	{
770	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
771	uinfo->count = 1;
772	return 0;
773	}
774
775	static int snd_rme9652_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
776	{
777	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
778
779	snd_rme9652_convert_to_aes(aes: &ucontrol->value.iec958, val: rme9652->creg_spdif);
780	return 0;
781	}
782
783	static int snd_rme9652_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
784	{
785	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
786	int change;
787	u32 val;
788
789	val = snd_rme9652_convert_from_aes(aes: &ucontrol->value.iec958);
790	guard(spinlock_irq)(l: &rme9652->lock);
791	change = val != rme9652->creg_spdif;
792	rme9652->creg_spdif = val;
793	return change;
794	}
795
796	static int snd_rme9652_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
797	{
798	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
799	uinfo->count = 1;
800	return 0;
801	}
802
803	static int snd_rme9652_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
804	{
805	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
806
807	snd_rme9652_convert_to_aes(aes: &ucontrol->value.iec958, val: rme9652->creg_spdif_stream);
808	return 0;
809	}
810
811	static int snd_rme9652_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
812	{
813	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
814	int change;
815	u32 val;
816
817	val = snd_rme9652_convert_from_aes(aes: &ucontrol->value.iec958);
818	guard(spinlock_irq)(l: &rme9652->lock);
819	change = val != rme9652->creg_spdif_stream;
820	rme9652->creg_spdif_stream = val;
821	rme9652->control_register &= ~(RME9652_PRO | RME9652_Dolby | RME9652_EMP);
822	rme9652_write(rme9652, RME9652_control_register, val: rme9652->control_register |= val);
823	return change;
824	}
825
826	static int snd_rme9652_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
827	{
828	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
829	uinfo->count = 1;
830	return 0;
831	}
832
833	static int snd_rme9652_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
834	{
835	ucontrol->value.iec958.status[0] = kcontrol->private_value;
836	return 0;
837	}
838
839	#define RME9652_ADAT1_IN(xname, xindex) \
840	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
841	.info = snd_rme9652_info_adat1_in, \
842	.get = snd_rme9652_get_adat1_in, \
843	.put = snd_rme9652_put_adat1_in }
844
845	static unsigned int rme9652_adat1_in(struct snd_rme9652 *rme9652)
846	{
847	if (rme9652->control_register & RME9652_ADAT1_INTERNAL)
848	return 1;
849	return 0;
850	}
851
852	static int rme9652_set_adat1_input(struct snd_rme9652 *rme9652, int internal)
853	{
854	int restart = 0;
855
856	if (internal) {
857	rme9652->control_register |= RME9652_ADAT1_INTERNAL;
858	} else {
859	rme9652->control_register &= ~RME9652_ADAT1_INTERNAL;
860	}
861
862	/* XXX do we actually need to stop the card when we do this ? */
863
864	restart = rme9652->running;
865	if (restart)
866	rme9652_stop(s: rme9652);
867
868	rme9652_write(rme9652, RME9652_control_register, val: rme9652->control_register);
869
870	if (restart)
871	rme9652_start(s: rme9652);
872
873	return 0;
874	}
875
876	static int snd_rme9652_info_adat1_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
877	{
878	static const char * const texts[2] = {"ADAT1", "Internal"};
879
880	return snd_ctl_enum_info(info: uinfo, channels: 1, items: 2, names: texts);
881	}
882
883	static int snd_rme9652_get_adat1_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
884	{
885	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
886
887	guard(spinlock_irq)(l: &rme9652->lock);
888	ucontrol->value.enumerated.item[0] = rme9652_adat1_in(rme9652);
889	return 0;
890	}
891
892	static int snd_rme9652_put_adat1_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
893	{
894	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
895	int change;
896	unsigned int val;
897
898	if (!snd_rme9652_use_is_exclusive(rme9652))
899	return -EBUSY;
900	val = ucontrol->value.enumerated.item[0] % 2;
901	guard(spinlock_irq)(l: &rme9652->lock);
902	change = val != rme9652_adat1_in(rme9652);
903	if (change)
904	rme9652_set_adat1_input(rme9652, internal: val);
905	return change;
906	}
907
908	#define RME9652_SPDIF_IN(xname, xindex) \
909	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
910	.info = snd_rme9652_info_spdif_in, \
911	.get = snd_rme9652_get_spdif_in, .put = snd_rme9652_put_spdif_in }
912
913	static unsigned int rme9652_spdif_in(struct snd_rme9652 *rme9652)
914	{
915	return rme9652_decode_spdif_in(rme9652->control_register &
916	RME9652_inp);
917	}
918
919	static int rme9652_set_spdif_input(struct snd_rme9652 *rme9652, int in)
920	{
921	int restart = 0;
922
923	rme9652->control_register &= ~RME9652_inp;
924	rme9652->control_register |= rme9652_encode_spdif_in(in);
925
926	restart = rme9652->running;
927	if (restart)
928	rme9652_stop(s: rme9652);
929
930	rme9652_write(rme9652, RME9652_control_register, val: rme9652->control_register);
931
932	if (restart)
933	rme9652_start(s: rme9652);
934
935	return 0;
936	}
937
938	static int snd_rme9652_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
939	{
940	static const char * const texts[3] = {"ADAT1", "Coaxial", "Internal"};
941
942	return snd_ctl_enum_info(info: uinfo, channels: 1, items: 3, names: texts);
943	}
944
945	static int snd_rme9652_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
946	{
947	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
948
949	guard(spinlock_irq)(l: &rme9652->lock);
950	ucontrol->value.enumerated.item[0] = rme9652_spdif_in(rme9652);
951	return 0;
952	}
953
954	static int snd_rme9652_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
955	{
956	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
957	int change;
958	unsigned int val;
959
960	if (!snd_rme9652_use_is_exclusive(rme9652))
961	return -EBUSY;
962	val = ucontrol->value.enumerated.item[0] % 3;
963	guard(spinlock_irq)(l: &rme9652->lock);
964	change = val != rme9652_spdif_in(rme9652);
965	if (change)
966	rme9652_set_spdif_input(rme9652, in: val);
967	return change;
968	}
969
970	#define RME9652_SPDIF_OUT(xname, xindex) \
971	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
972	.info = snd_rme9652_info_spdif_out, \
973	.get = snd_rme9652_get_spdif_out, .put = snd_rme9652_put_spdif_out }
974
975	static int rme9652_spdif_out(struct snd_rme9652 *rme9652)
976	{
977	return (rme9652->control_register & RME9652_opt_out) ? 1 : 0;
978	}
979
980	static int rme9652_set_spdif_output(struct snd_rme9652 *rme9652, int out)
981	{
982	int restart = 0;
983
984	if (out) {
985	rme9652->control_register |= RME9652_opt_out;
986	} else {
987	rme9652->control_register &= ~RME9652_opt_out;
988	}
989
990	restart = rme9652->running;
991	if (restart)
992	rme9652_stop(s: rme9652);
993
994	rme9652_write(rme9652, RME9652_control_register, val: rme9652->control_register);
995
996	if (restart)
997	rme9652_start(s: rme9652);
998
999	return 0;
1000	}
1001
1002	#define snd_rme9652_info_spdif_out snd_ctl_boolean_mono_info
1003
1004	static int snd_rme9652_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1005	{
1006	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1007
1008	guard(spinlock_irq)(l: &rme9652->lock);
1009	ucontrol->value.integer.value[0] = rme9652_spdif_out(rme9652);
1010	return 0;
1011	}
1012
1013	static int snd_rme9652_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1014	{
1015	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1016	int change;
1017	unsigned int val;
1018
1019	if (!snd_rme9652_use_is_exclusive(rme9652))
1020	return -EBUSY;
1021	val = ucontrol->value.integer.value[0] & 1;
1022	guard(spinlock_irq)(l: &rme9652->lock);
1023	change = (int)val != rme9652_spdif_out(rme9652);
1024	rme9652_set_spdif_output(rme9652, out: val);
1025	return change;
1026	}
1027
1028	#define RME9652_SYNC_MODE(xname, xindex) \
1029	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1030	.info = snd_rme9652_info_sync_mode, \
1031	.get = snd_rme9652_get_sync_mode, .put = snd_rme9652_put_sync_mode }
1032
1033	static int rme9652_sync_mode(struct snd_rme9652 *rme9652)
1034	{
1035	if (rme9652->control_register & RME9652_wsel) {
1036	return 2;
1037	} else if (rme9652->control_register & RME9652_Master) {
1038	return 1;
1039	} else {
1040	return 0;
1041	}
1042	}
1043
1044	static int rme9652_set_sync_mode(struct snd_rme9652 *rme9652, int mode)
1045	{
1046	int restart = 0;
1047
1048	switch (mode) {
1049	case 0:
1050	rme9652->control_register &=
1051	~(RME9652_Master | RME9652_wsel);
1052	break;
1053	case 1:
1054	rme9652->control_register =
1055	(rme9652->control_register & ~RME9652_wsel) | RME9652_Master;
1056	break;
1057	case 2:
1058	rme9652->control_register |=
1059	(RME9652_Master | RME9652_wsel);
1060	break;
1061	}
1062
1063	restart = rme9652->running;
1064	if (restart)
1065	rme9652_stop(s: rme9652);
1066
1067	rme9652_write(rme9652, RME9652_control_register, val: rme9652->control_register);
1068
1069	if (restart)
1070	rme9652_start(s: rme9652);
1071
1072	return 0;
1073	}
1074
1075	static int snd_rme9652_info_sync_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1076	{
1077	static const char * const texts[3] = {
1078	"AutoSync", "Master", "Word Clock"
1079	};
1080
1081	return snd_ctl_enum_info(info: uinfo, channels: 1, items: 3, names: texts);
1082	}
1083
1084	static int snd_rme9652_get_sync_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1085	{
1086	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1087
1088	guard(spinlock_irq)(l: &rme9652->lock);
1089	ucontrol->value.enumerated.item[0] = rme9652_sync_mode(rme9652);
1090	return 0;
1091	}
1092
1093	static int snd_rme9652_put_sync_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1094	{
1095	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1096	int change;
1097	unsigned int val;
1098
1099	val = ucontrol->value.enumerated.item[0] % 3;
1100	guard(spinlock_irq)(l: &rme9652->lock);
1101	change = (int)val != rme9652_sync_mode(rme9652);
1102	rme9652_set_sync_mode(rme9652, mode: val);
1103	return change;
1104	}
1105
1106	#define RME9652_SYNC_PREF(xname, xindex) \
1107	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1108	.info = snd_rme9652_info_sync_pref, \
1109	.get = snd_rme9652_get_sync_pref, .put = snd_rme9652_put_sync_pref }
1110
1111	static int rme9652_sync_pref(struct snd_rme9652 *rme9652)
1112	{
1113	switch (rme9652->control_register & RME9652_SyncPref_Mask) {
1114	case RME9652_SyncPref_ADAT1:
1115	return RME9652_SYNC_FROM_ADAT1;
1116	case RME9652_SyncPref_ADAT2:
1117	return RME9652_SYNC_FROM_ADAT2;
1118	case RME9652_SyncPref_ADAT3:
1119	return RME9652_SYNC_FROM_ADAT3;
1120	case RME9652_SyncPref_SPDIF:
1121	return RME9652_SYNC_FROM_SPDIF;
1122	}
1123	/* Not reachable */
1124	return 0;
1125	}
1126
1127	static int rme9652_set_sync_pref(struct snd_rme9652 *rme9652, int pref)
1128	{
1129	int restart;
1130
1131	rme9652->control_register &= ~RME9652_SyncPref_Mask;
1132	switch (pref) {
1133	case RME9652_SYNC_FROM_ADAT1:
1134	rme9652->control_register |= RME9652_SyncPref_ADAT1;
1135	break;
1136	case RME9652_SYNC_FROM_ADAT2:
1137	rme9652->control_register |= RME9652_SyncPref_ADAT2;
1138	break;
1139	case RME9652_SYNC_FROM_ADAT3:
1140	rme9652->control_register |= RME9652_SyncPref_ADAT3;
1141	break;
1142	case RME9652_SYNC_FROM_SPDIF:
1143	rme9652->control_register |= RME9652_SyncPref_SPDIF;
1144	break;
1145	}
1146
1147	restart = rme9652->running;
1148	if (restart)
1149	rme9652_stop(s: rme9652);
1150
1151	rme9652_write(rme9652, RME9652_control_register, val: rme9652->control_register);
1152
1153	if (restart)
1154	rme9652_start(s: rme9652);
1155
1156	return 0;
1157	}
1158
1159	static int snd_rme9652_info_sync_pref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1160	{
1161	static const char * const texts[4] = {
1162	"IEC958 In", "ADAT1 In", "ADAT2 In", "ADAT3 In"
1163	};
1164	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1165
1166	return snd_ctl_enum_info(info: uinfo, channels: 1,
1167	items: rme9652->ss_channels == RME9652_NCHANNELS ? 4 : 3,
1168	names: texts);
1169	}
1170
1171	static int snd_rme9652_get_sync_pref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1172	{
1173	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1174
1175	guard(spinlock_irq)(l: &rme9652->lock);
1176	ucontrol->value.enumerated.item[0] = rme9652_sync_pref(rme9652);
1177	return 0;
1178	}
1179
1180	static int snd_rme9652_put_sync_pref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1181	{
1182	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1183	int change, max;
1184	unsigned int val;
1185
1186	if (!snd_rme9652_use_is_exclusive(rme9652))
1187	return -EBUSY;
1188	max = rme9652->ss_channels == RME9652_NCHANNELS ? 4 : 3;
1189	val = ucontrol->value.enumerated.item[0] % max;
1190	guard(spinlock_irq)(l: &rme9652->lock);
1191	change = (int)val != rme9652_sync_pref(rme9652);
1192	rme9652_set_sync_pref(rme9652, pref: val);
1193	return change;
1194	}
1195
1196	static int snd_rme9652_info_thru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1197	{
1198	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1199	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1200	uinfo->count = rme9652->ss_channels;
1201	uinfo->value.integer.min = 0;
1202	uinfo->value.integer.max = 1;
1203	return 0;
1204	}
1205
1206	static int snd_rme9652_get_thru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1207	{
1208	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1209	unsigned int k;
1210	u32 thru_bits = rme9652->thru_bits;
1211
1212	for (k = 0; k < rme9652->ss_channels; ++k) {
1213	ucontrol->value.integer.value[k] = !!(thru_bits & (1 << k));
1214	}
1215	return 0;
1216	}
1217
1218	static int snd_rme9652_put_thru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1219	{
1220	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1221	int change;
1222	unsigned int chn;
1223	u32 thru_bits = 0;
1224
1225	if (!snd_rme9652_use_is_exclusive(rme9652))
1226	return -EBUSY;
1227
1228	for (chn = 0; chn < rme9652->ss_channels; ++chn) {
1229	if (ucontrol->value.integer.value[chn])
1230	thru_bits |= 1 << chn;
1231	}
1232
1233	guard(spinlock_irq)(l: &rme9652->lock);
1234	change = thru_bits ^ rme9652->thru_bits;
1235	if (change) {
1236	for (chn = 0; chn < rme9652->ss_channels; ++chn) {
1237	if (!(change & (1 << chn)))
1238	continue;
1239	rme9652_set_thru(rme9652,channel: chn,enable: thru_bits&(1<<chn));
1240	}
1241	}
1242	return !!change;
1243	}
1244
1245	#define RME9652_PASSTHRU(xname, xindex) \
1246	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1247	.info = snd_rme9652_info_passthru, \
1248	.put = snd_rme9652_put_passthru, \
1249	.get = snd_rme9652_get_passthru }
1250
1251	#define snd_rme9652_info_passthru snd_ctl_boolean_mono_info
1252
1253	static int snd_rme9652_get_passthru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1254	{
1255	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1256
1257	guard(spinlock_irq)(l: &rme9652->lock);
1258	ucontrol->value.integer.value[0] = rme9652->passthru;
1259	return 0;
1260	}
1261
1262	static int snd_rme9652_put_passthru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1263	{
1264	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1265	int change;
1266	unsigned int val;
1267	int err = 0;
1268
1269	if (!snd_rme9652_use_is_exclusive(rme9652))
1270	return -EBUSY;
1271
1272	val = ucontrol->value.integer.value[0] & 1;
1273	guard(spinlock_irq)(l: &rme9652->lock);
1274	change = (ucontrol->value.integer.value[0] != rme9652->passthru);
1275	if (change)
1276	err = rme9652_set_passthru(rme9652, onoff: val);
1277	return err ? err : change;
1278	}
1279
1280	/* Read-only switches */
1281
1282	#define RME9652_SPDIF_RATE(xname, xindex) \
1283	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1284	.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1285	.info = snd_rme9652_info_spdif_rate, \
1286	.get = snd_rme9652_get_spdif_rate }
1287
1288	static int snd_rme9652_info_spdif_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1289	{
1290	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1291	uinfo->count = 1;
1292	uinfo->value.integer.min = 0;
1293	uinfo->value.integer.max = 96000;
1294	return 0;
1295	}
1296
1297	static int snd_rme9652_get_spdif_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1298	{
1299	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1300
1301	guard(spinlock_irq)(l: &rme9652->lock);
1302	ucontrol->value.integer.value[0] = rme9652_spdif_sample_rate(s: rme9652);
1303	return 0;
1304	}
1305
1306	#define RME9652_ADAT_SYNC(xname, xindex, xidx) \
1307	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1308	.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1309	.info = snd_rme9652_info_adat_sync, \
1310	.get = snd_rme9652_get_adat_sync, .private_value = xidx }
1311
1312	static int snd_rme9652_info_adat_sync(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1313	{
1314	static const char * const texts[4] = {
1315	"No Lock", "Lock", "No Lock Sync", "Lock Sync"
1316	};
1317
1318	return snd_ctl_enum_info(info: uinfo, channels: 1, items: 4, names: texts);
1319	}
1320
1321	static int snd_rme9652_get_adat_sync(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1322	{
1323	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1324	unsigned int mask1, mask2, val;
1325
1326	switch (kcontrol->private_value) {
1327	case 0: mask1 = RME9652_lock_0; mask2 = RME9652_sync_0; break;
1328	case 1: mask1 = RME9652_lock_1; mask2 = RME9652_sync_1; break;
1329	case 2: mask1 = RME9652_lock_2; mask2 = RME9652_sync_2; break;
1330	default: return -EINVAL;
1331	}
1332	val = rme9652_read(rme9652, RME9652_status_register);
1333	ucontrol->value.enumerated.item[0] = (val & mask1) ? 1 : 0;
1334	ucontrol->value.enumerated.item[0] |= (val & mask2) ? 2 : 0;
1335	return 0;
1336	}
1337
1338	#define RME9652_TC_VALID(xname, xindex) \
1339	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1340	.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
1341	.info = snd_rme9652_info_tc_valid, \
1342	.get = snd_rme9652_get_tc_valid }
1343
1344	#define snd_rme9652_info_tc_valid snd_ctl_boolean_mono_info
1345
1346	static int snd_rme9652_get_tc_valid(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1347	{
1348	struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);
1349
1350	ucontrol->value.integer.value[0] =
1351	(rme9652_read(rme9652, RME9652_status_register) & RME9652_tc_valid) ? 1 : 0;
1352	return 0;
1353	}
1354
1355	#ifdef ALSA_HAS_STANDARD_WAY_OF_RETURNING_TIMECODE
1356
1357	/* FIXME: this routine needs a port to the new control API --jk */
1358
1359	static int snd_rme9652_get_tc_value(void *private_data,
1360	snd_kswitch_t *kswitch,
1361	snd_switch_t *uswitch)
1362	{
1363	struct snd_rme9652 *s = (struct snd_rme9652 *) private_data;
1364	u32 value;
1365	int i;
1366
1367	uswitch->type = SNDRV_SW_TYPE_DWORD;
1368
1369	if ((rme9652_read(s, RME9652_status_register) &
1370	RME9652_tc_valid) == 0) {
1371	uswitch->value.data32[0] = 0;
1372	return 0;
1373	}
1374
1375	/* timecode request */
1376
1377	rme9652_write(s, RME9652_time_code, 0);
1378
1379	/* XXX bug alert: loop-based timing !!!! */
1380
1381	for (i = 0; i < 50; i++) {
1382	if (!(rme9652_read(s, i * 4) & RME9652_tc_busy))
1383	break;
1384	}
1385
1386	if (!(rme9652_read(s, i * 4) & RME9652_tc_busy)) {
1387	return -EIO;
1388	}
1389
1390	value = 0;
1391
1392	for (i = 0; i < 32; i++) {
1393	value >>= 1;
1394
1395	if (rme9652_read(s, i * 4) & RME9652_tc_out)
1396	value |= 0x80000000;
1397	}
1398
1399	if (value > 2 * 60 * 48000) {
1400	value -= 2 * 60 * 48000;
1401	} else {
1402	value = 0;
1403	}
1404
1405	uswitch->value.data32[0] = value;
1406
1407	return 0;
1408	}
1409
1410	#endif /* ALSA_HAS_STANDARD_WAY_OF_RETURNING_TIMECODE */
1411
1412	static const struct snd_kcontrol_new snd_rme9652_controls[] = {
1413	{
1414	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1415	.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1416	.info = snd_rme9652_control_spdif_info,
1417	.get = snd_rme9652_control_spdif_get,
1418	.put = snd_rme9652_control_spdif_put,
1419	},
1420	{
1421	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1422	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1423	.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1424	.info = snd_rme9652_control_spdif_stream_info,
1425	.get = snd_rme9652_control_spdif_stream_get,
1426	.put = snd_rme9652_control_spdif_stream_put,
1427	},
1428	{
1429	.access = SNDRV_CTL_ELEM_ACCESS_READ,
1430	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1431	.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1432	.info = snd_rme9652_control_spdif_mask_info,
1433	.get = snd_rme9652_control_spdif_mask_get,
1434	.private_value = IEC958_AES0_NONAUDIO |
1435	IEC958_AES0_PROFESSIONAL |
1436	IEC958_AES0_CON_EMPHASIS,
1437	},
1438	{
1439	.access = SNDRV_CTL_ELEM_ACCESS_READ,
1440	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1441	.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
1442	.info = snd_rme9652_control_spdif_mask_info,
1443	.get = snd_rme9652_control_spdif_mask_get,
1444	.private_value = IEC958_AES0_NONAUDIO |
1445	IEC958_AES0_PROFESSIONAL |
1446	IEC958_AES0_PRO_EMPHASIS,
1447	},
1448	RME9652_SPDIF_IN("IEC958 Input Connector", 0),
1449	RME9652_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
1450	RME9652_SYNC_MODE("Sync Mode", 0),
1451	RME9652_SYNC_PREF("Preferred Sync Source", 0),
1452	{
1453	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1454	.name = "Channels Thru",
1455	.index = 0,
1456	.info = snd_rme9652_info_thru,
1457	.get = snd_rme9652_get_thru,
1458	.put = snd_rme9652_put_thru,
1459	},
1460	RME9652_SPDIF_RATE("IEC958 Sample Rate", 0),
1461	RME9652_ADAT_SYNC("ADAT1 Sync Check", 0, 0),
1462	RME9652_ADAT_SYNC("ADAT2 Sync Check", 0, 1),
1463	RME9652_TC_VALID("Timecode Valid", 0),
1464	RME9652_PASSTHRU("Passthru", 0)
1465	};
1466
1467	static const struct snd_kcontrol_new snd_rme9652_adat3_check =
1468	RME9652_ADAT_SYNC("ADAT3 Sync Check", 0, 2);
1469
1470	static const struct snd_kcontrol_new snd_rme9652_adat1_input =
1471	RME9652_ADAT1_IN("ADAT1 Input Source", 0);
1472
1473	static int snd_rme9652_create_controls(struct snd_card *card, struct snd_rme9652 *rme9652)
1474	{
1475	unsigned int idx;
1476	int err;
1477	struct snd_kcontrol *kctl;
1478
1479	for (idx = 0; idx < ARRAY_SIZE(snd_rme9652_controls); idx++) {
1480	kctl = snd_ctl_new1(kcontrolnew: &snd_rme9652_controls[idx], private_data: rme9652);
1481	err = snd_ctl_add(card, kcontrol: kctl);
1482	if (err < 0)
1483	return err;
1484	if (idx == 1) /* IEC958 (S/PDIF) Stream */
1485	rme9652->spdif_ctl = kctl;
1486	}
1487
1488	if (rme9652->ss_channels == RME9652_NCHANNELS) {
1489	kctl = snd_ctl_new1(kcontrolnew: &snd_rme9652_adat3_check, private_data: rme9652);
1490	err = snd_ctl_add(card, kcontrol: kctl);
1491	if (err < 0)
1492	return err;
1493	}
1494
1495	if (rme9652->hw_rev >= 15) {
1496	kctl = snd_ctl_new1(kcontrolnew: &snd_rme9652_adat1_input, private_data: rme9652);
1497	err = snd_ctl_add(card, kcontrol: kctl);
1498	if (err < 0)
1499	return err;
1500	}
1501
1502	return 0;
1503	}
1504
1505	/*------------------------------------------------------------
1506	/proc interface
1507	------------------------------------------------------------*/
1508
1509	static void
1510	snd_rme9652_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1511	{
1512	struct snd_rme9652 *rme9652 = (struct snd_rme9652 *) entry->private_data;
1513	u32 thru_bits = rme9652->thru_bits;
1514	int show_auto_sync_source = 0;
1515	int i;
1516	unsigned int status;
1517	int x;
1518
1519	status = rme9652_read(rme9652, RME9652_status_register);
1520
1521	snd_iprintf(buffer, "%s (Card #%d)\n", rme9652->card_name, rme9652->card->number + 1);
1522	snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
1523	rme9652->capture_buffer, rme9652->playback_buffer);
1524	snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
1525	rme9652->irq, rme9652->port, (unsigned long)rme9652->iobase);
1526	snd_iprintf(buffer, "Control register: %x\n", rme9652->control_register);
1527
1528	snd_iprintf(buffer, "\n");
1529
1530	x = 1 << (6 + rme9652_decode_latency(rme9652->control_register &
1531	RME9652_latency));
1532
1533	snd_iprintf(buffer, "Latency: %d samples (2 periods of %lu bytes)\n",
1534	x, (unsigned long) rme9652->period_bytes);
1535	snd_iprintf(buffer, "Hardware pointer (frames): %ld\n",
1536	rme9652_hw_pointer(rme9652));
1537	snd_iprintf(buffer, "Passthru: %s\n", str_yes_no(rme9652->passthru));
1538
1539	if ((rme9652->control_register & (RME9652_Master | RME9652_wsel)) == 0) {
1540	snd_iprintf(buffer, "Clock mode: autosync\n");
1541	show_auto_sync_source = 1;
1542	} else if (rme9652->control_register & RME9652_wsel) {
1543	if (status & RME9652_wsel_rd) {
1544	snd_iprintf(buffer, "Clock mode: word clock\n");
1545	} else {
1546	snd_iprintf(buffer, "Clock mode: word clock (no signal)\n");
1547	}
1548	} else {
1549	snd_iprintf(buffer, "Clock mode: master\n");
1550	}
1551
1552	if (show_auto_sync_source) {
1553	switch (rme9652->control_register & RME9652_SyncPref_Mask) {
1554	case RME9652_SyncPref_ADAT1:
1555	snd_iprintf(buffer, "Pref. sync source: ADAT1\n");
1556	break;
1557	case RME9652_SyncPref_ADAT2:
1558	snd_iprintf(buffer, "Pref. sync source: ADAT2\n");
1559	break;
1560	case RME9652_SyncPref_ADAT3:
1561	snd_iprintf(buffer, "Pref. sync source: ADAT3\n");
1562	break;
1563	case RME9652_SyncPref_SPDIF:
1564	snd_iprintf(buffer, "Pref. sync source: IEC958\n");
1565	break;
1566	default:
1567	snd_iprintf(buffer, "Pref. sync source: ???\n");
1568	}
1569	}
1570
1571	if (rme9652->hw_rev >= 15)
1572	snd_iprintf(buffer, "\nADAT1 Input source: %s\n",
1573	(rme9652->control_register & RME9652_ADAT1_INTERNAL) ?
1574	"Internal" : "ADAT1 optical");
1575
1576	snd_iprintf(buffer, "\n");
1577
1578	switch (rme9652_decode_spdif_in(rme9652->control_register &
1579	RME9652_inp)) {
1580	case RME9652_SPDIFIN_OPTICAL:
1581	snd_iprintf(buffer, "IEC958 input: ADAT1\n");
1582	break;
1583	case RME9652_SPDIFIN_COAXIAL:
1584	snd_iprintf(buffer, "IEC958 input: Coaxial\n");
1585	break;
1586	case RME9652_SPDIFIN_INTERN:
1587	snd_iprintf(buffer, "IEC958 input: Internal\n");
1588	break;
1589	default:
1590	snd_iprintf(buffer, "IEC958 input: ???\n");
1591	break;
1592	}
1593
1594	if (rme9652->control_register & RME9652_opt_out) {
1595	snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
1596	} else {
1597	snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
1598	}
1599
1600	if (rme9652->control_register & RME9652_PRO) {
1601	snd_iprintf(buffer, "IEC958 quality: Professional\n");
1602	} else {
1603	snd_iprintf(buffer, "IEC958 quality: Consumer\n");
1604	}
1605
1606	if (rme9652->control_register & RME9652_EMP) {
1607	snd_iprintf(buffer, "IEC958 emphasis: on\n");
1608	} else {
1609	snd_iprintf(buffer, "IEC958 emphasis: off\n");
1610	}
1611
1612	if (rme9652->control_register & RME9652_Dolby) {
1613	snd_iprintf(buffer, "IEC958 Dolby: on\n");
1614	} else {
1615	snd_iprintf(buffer, "IEC958 Dolby: off\n");
1616	}
1617
1618	i = rme9652_spdif_sample_rate(s: rme9652);
1619
1620	if (i < 0) {
1621	snd_iprintf(buffer,
1622	"IEC958 sample rate: error flag set\n");
1623	} else if (i == 0) {
1624	snd_iprintf(buffer, "IEC958 sample rate: undetermined\n");
1625	} else {
1626	snd_iprintf(buffer, "IEC958 sample rate: %d\n", i);
1627	}
1628
1629	snd_iprintf(buffer, "\n");
1630
1631	snd_iprintf(buffer, "ADAT Sample rate: %dHz\n",
1632	rme9652_adat_sample_rate(rme9652));
1633
1634	/* Sync Check */
1635
1636	x = status & RME9652_sync_0;
1637	if (status & RME9652_lock_0) {
1638	snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
1639	} else {
1640	snd_iprintf(buffer, "ADAT1: No Lock\n");
1641	}
1642
1643	x = status & RME9652_sync_1;
1644	if (status & RME9652_lock_1) {
1645	snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
1646	} else {
1647	snd_iprintf(buffer, "ADAT2: No Lock\n");
1648	}
1649
1650	x = status & RME9652_sync_2;
1651	if (status & RME9652_lock_2) {
1652	snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
1653	} else {
1654	snd_iprintf(buffer, "ADAT3: No Lock\n");
1655	}
1656
1657	snd_iprintf(buffer, "\n");
1658
1659	snd_iprintf(buffer, "Timecode signal: %s\n",
1660	str_yes_no(status & RME9652_tc_valid));
1661
1662	/* thru modes */
1663
1664	snd_iprintf(buffer, "Punch Status:\n\n");
1665
1666	for (i = 0; i < rme9652->ss_channels; i++) {
1667	if (thru_bits & (1 << i)) {
1668	snd_iprintf(buffer, "%2d: on ", i + 1);
1669	} else {
1670	snd_iprintf(buffer, "%2d: off ", i + 1);
1671	}
1672
1673	if (((i + 1) % 8) == 0) {
1674	snd_iprintf(buffer, "\n");
1675	}
1676	}
1677
1678	snd_iprintf(buffer, "\n");
1679	}
1680
1681	static void snd_rme9652_proc_init(struct snd_rme9652 *rme9652)
1682	{
1683	snd_card_ro_proc_new(card: rme9652->card, name: "rme9652", private_data: rme9652,
1684	read: snd_rme9652_proc_read);
1685	}
1686
1687	static void snd_rme9652_card_free(struct snd_card *card)
1688	{
1689	struct snd_rme9652 *rme9652 = (struct snd_rme9652 *) card->private_data;
1690
1691	if (rme9652->irq >= 0)
1692	rme9652_stop(s: rme9652);
1693	}
1694
1695	static int snd_rme9652_initialize_memory(struct snd_rme9652 *rme9652)
1696	{
1697	struct snd_dma_buffer *capture_dma, *playback_dma;
1698
1699	capture_dma = snd_hammerfall_get_buffer(pci: rme9652->pci, RME9652_DMA_AREA_BYTES);
1700	playback_dma = snd_hammerfall_get_buffer(pci: rme9652->pci, RME9652_DMA_AREA_BYTES);
1701	if (!capture_dma || !playback_dma) {
1702	dev_err(rme9652->card->dev,
1703	"%s: no buffers available\n", rme9652->card_name);
1704	return -ENOMEM;
1705	}
1706
1707	/* copy to the own data for alignment */
1708	rme9652->capture_dma_buf = *capture_dma;
1709	rme9652->playback_dma_buf = *playback_dma;
1710
1711	/* Align to bus-space 64K boundary */
1712	rme9652->capture_dma_buf.addr = ALIGN(capture_dma->addr, 0x10000ul);
1713	rme9652->playback_dma_buf.addr = ALIGN(playback_dma->addr, 0x10000ul);
1714
1715	/* Tell the card where it is */
1716	rme9652_write(rme9652, RME9652_rec_buffer, val: rme9652->capture_dma_buf.addr);
1717	rme9652_write(rme9652, RME9652_play_buffer, val: rme9652->playback_dma_buf.addr);
1718
1719	rme9652->capture_dma_buf.area += rme9652->capture_dma_buf.addr - capture_dma->addr;
1720	rme9652->playback_dma_buf.area += rme9652->playback_dma_buf.addr - playback_dma->addr;
1721	rme9652->capture_buffer = rme9652->capture_dma_buf.area;
1722	rme9652->playback_buffer = rme9652->playback_dma_buf.area;
1723
1724	return 0;
1725	}
1726
1727	static void snd_rme9652_set_defaults(struct snd_rme9652 *rme9652)
1728	{
1729	unsigned int k;
1730
1731	/* ASSUMPTION: rme9652->lock is either held, or
1732	there is no need to hold it (e.g. during module
1733	initialization).
1734	*/
1735
1736	/* set defaults:
1737
1738	SPDIF Input via Coax
1739	autosync clock mode
1740	maximum latency (7 = 8192 samples, 64Kbyte buffer,
1741	which implies 2 4096 sample, 32Kbyte periods).
1742
1743	if rev 1.5, initialize the S/PDIF receiver.
1744
1745	*/
1746
1747	rme9652->control_register =
1748	RME9652_inp_0 | rme9652_encode_latency(7);
1749
1750	rme9652_write(rme9652, RME9652_control_register, val: rme9652->control_register);
1751
1752	rme9652_reset_hw_pointer(rme9652);
1753	rme9652_compute_period_size(rme9652);
1754
1755	/* default: thru off for all channels */
1756
1757	for (k = 0; k < RME9652_NCHANNELS; ++k)
1758	rme9652_write(rme9652, RME9652_thru_base + k * 4, val: 0);
1759
1760	rme9652->thru_bits = 0;
1761	rme9652->passthru = 0;
1762
1763	/* set a default rate so that the channel map is set up */
1764
1765	rme9652_set_rate(rme9652, rate: 48000);
1766	}
1767
1768	static irqreturn_t snd_rme9652_interrupt(int irq, void *dev_id)
1769	{
1770	struct snd_rme9652 *rme9652 = (struct snd_rme9652 *) dev_id;
1771
1772	if (!(rme9652_read(rme9652, RME9652_status_register) & RME9652_IRQ)) {
1773	return IRQ_NONE;
1774	}
1775
1776	rme9652_write(rme9652, RME9652_irq_clear, val: 0);
1777
1778	if (rme9652->capture_substream) {
1779	snd_pcm_period_elapsed(substream: rme9652->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
1780	}
1781
1782	if (rme9652->playback_substream) {
1783	snd_pcm_period_elapsed(substream: rme9652->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
1784	}
1785	return IRQ_HANDLED;
1786	}
1787
1788	static snd_pcm_uframes_t snd_rme9652_hw_pointer(struct snd_pcm_substream *substream)
1789	{
1790	struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
1791	return rme9652_hw_pointer(rme9652);
1792	}
1793
1794	static signed char *rme9652_channel_buffer_location(struct snd_rme9652 *rme9652,
1795	int stream,
1796	int channel)
1797
1798	{
1799	int mapped_channel;
1800
1801	if (snd_BUG_ON(channel < 0 || channel >= RME9652_NCHANNELS))
1802	return NULL;
1803
1804	mapped_channel = rme9652->channel_map[channel];
1805	if (mapped_channel < 0)
1806	return NULL;
1807
1808	if (stream == SNDRV_PCM_STREAM_CAPTURE) {
1809	return rme9652->capture_buffer +
1810	(mapped_channel * RME9652_CHANNEL_BUFFER_BYTES);
1811	} else {
1812	return rme9652->playback_buffer +
1813	(mapped_channel * RME9652_CHANNEL_BUFFER_BYTES);
1814	}
1815	}
1816
1817	static int snd_rme9652_playback_copy(struct snd_pcm_substream *substream,
1818	int channel, unsigned long pos,
1819	struct iov_iter *src, unsigned long count)
1820	{
1821	struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
1822	signed char *channel_buf;
1823
1824	if (snd_BUG_ON(pos + count > RME9652_CHANNEL_BUFFER_BYTES))
1825	return -EINVAL;
1826
1827	channel_buf = rme9652_channel_buffer_location (rme9652,
1828	stream: substream->pstr->stream,
1829	channel);
1830	if (snd_BUG_ON(!channel_buf))
1831	return -EIO;
1832	if (copy_from_iter(addr: channel_buf + pos, bytes: count, i: src) != count)
1833	return -EFAULT;
1834	return 0;
1835	}
1836
1837	static int snd_rme9652_capture_copy(struct snd_pcm_substream *substream,
1838	int channel, unsigned long pos,
1839	struct iov_iter *dst, unsigned long count)
1840	{
1841	struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
1842	signed char *channel_buf;
1843
1844	if (snd_BUG_ON(pos + count > RME9652_CHANNEL_BUFFER_BYTES))
1845	return -EINVAL;
1846
1847	channel_buf = rme9652_channel_buffer_location (rme9652,
1848	stream: substream->pstr->stream,
1849	channel);
1850	if (snd_BUG_ON(!channel_buf))
1851	return -EIO;
1852	if (copy_to_iter(addr: channel_buf + pos, bytes: count, i: dst) != count)
1853	return -EFAULT;
1854	return 0;
1855	}
1856
1857	static int snd_rme9652_hw_silence(struct snd_pcm_substream *substream,
1858	int channel, unsigned long pos,
1859	unsigned long count)
1860	{
1861	struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
1862	signed char *channel_buf;
1863
1864	channel_buf = rme9652_channel_buffer_location (rme9652,
1865	stream: substream->pstr->stream,
1866	channel);
1867	if (snd_BUG_ON(!channel_buf))
1868	return -EIO;
1869	memset(channel_buf + pos, 0, count);
1870	return 0;
1871	}
1872
1873	static int snd_rme9652_reset(struct snd_pcm_substream *substream)
1874	{
1875	struct snd_pcm_runtime *runtime = substream->runtime;
1876	struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
1877	struct snd_pcm_substream *other;
1878	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1879	other = rme9652->capture_substream;
1880	else
1881	other = rme9652->playback_substream;
1882	if (rme9652->running)
1883	runtime->status->hw_ptr = rme9652_hw_pointer(rme9652);
1884	else
1885	runtime->status->hw_ptr = 0;
1886	if (other) {
1887	struct snd_pcm_substream *s;
1888	struct snd_pcm_runtime *oruntime = other->runtime;
1889	snd_pcm_group_for_each_entry(s, substream) {
1890	if (s == other) {
1891	oruntime->status->hw_ptr = runtime->status->hw_ptr;
1892	break;
1893	}
1894	}
1895	}
1896	return 0;
1897	}
1898
1899	static int snd_rme9652_hw_params(struct snd_pcm_substream *substream,
1900	struct snd_pcm_hw_params *params)
1901	{
1902	struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
1903	int err;
1904	pid_t this_pid;
1905	pid_t other_pid;
1906
1907	scoped_guard(spinlock_irq, &rme9652->lock) {
1908
1909	if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1910	rme9652->control_register &= ~(RME9652_PRO | RME9652_Dolby | RME9652_EMP);
1911	rme9652_write(rme9652, RME9652_control_register, val: rme9652->control_register |= rme9652->creg_spdif_stream);
1912	this_pid = rme9652->playback_pid;
1913	other_pid = rme9652->capture_pid;
1914	} else {
1915	this_pid = rme9652->capture_pid;
1916	other_pid = rme9652->playback_pid;
1917	}
1918
1919	if ((other_pid > 0) && (this_pid != other_pid)) {
1920
1921	/* The other stream is open, and not by the same
1922	task as this one. Make sure that the parameters
1923	that matter are the same.
1924	*/
1925
1926	if ((int)params_rate(p: params) !=
1927	rme9652_adat_sample_rate(rme9652)) {
1928	_snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
1929	return -EBUSY;
1930	}
1931
1932	if (params_period_size(p: params) != rme9652->period_bytes / 4) {
1933	_snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1934	return -EBUSY;
1935	}
1936
1937	/* We're fine. */
1938	return 0;
1939	}
1940	}
1941
1942	/* how to make sure that the rate matches an externally-set one ?
1943	*/
1944
1945	err = rme9652_set_rate(rme9652, rate: params_rate(p: params));
1946	if (err < 0) {
1947	_snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
1948	return err;
1949	}
1950
1951	err = rme9652_set_interrupt_interval(s: rme9652, frames: params_period_size(p: params));
1952	if (err < 0) {
1953	_snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1954	return err;
1955	}
1956
1957	return 0;
1958	}
1959
1960	static int snd_rme9652_channel_info(struct snd_pcm_substream *substream,
1961	struct snd_pcm_channel_info *info)
1962	{
1963	struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
1964	int chn;
1965
1966	if (snd_BUG_ON(info->channel >= RME9652_NCHANNELS))
1967	return -EINVAL;
1968
1969	chn = rme9652->channel_map[array_index_nospec(info->channel,
1970	RME9652_NCHANNELS)];
1971	if (chn < 0)
1972	return -EINVAL;
1973
1974	info->offset = chn * RME9652_CHANNEL_BUFFER_BYTES;
1975	info->first = 0;
1976	info->step = 32;
1977	return 0;
1978	}
1979
1980	static int snd_rme9652_ioctl(struct snd_pcm_substream *substream,
1981	unsigned int cmd, void *arg)
1982	{
1983	switch (cmd) {
1984	case SNDRV_PCM_IOCTL1_RESET:
1985	{
1986	return snd_rme9652_reset(substream);
1987	}
1988	case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
1989	{
1990	struct snd_pcm_channel_info *info = arg;
1991	return snd_rme9652_channel_info(substream, info);
1992	}
1993	default:
1994	break;
1995	}
1996
1997	return snd_pcm_lib_ioctl(substream, cmd, arg);
1998	}
1999
2000	static void rme9652_silence_playback(struct snd_rme9652 *rme9652)
2001	{
2002	memset(rme9652->playback_buffer, 0, RME9652_DMA_AREA_BYTES);
2003	}
2004
2005	static int snd_rme9652_trigger(struct snd_pcm_substream *substream,
2006	int cmd)
2007	{
2008	struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
2009	struct snd_pcm_substream *other;
2010	int running;
2011
2012	guard(spinlock)(l: &rme9652->lock);
2013	running = rme9652->running;
2014	switch (cmd) {
2015	case SNDRV_PCM_TRIGGER_START:
2016	running |= 1 << substream->stream;
2017	break;
2018	case SNDRV_PCM_TRIGGER_STOP:
2019	running &= ~(1 << substream->stream);
2020	break;
2021	default:
2022	snd_BUG();
2023	return -EINVAL;
2024	}
2025	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2026	other = rme9652->capture_substream;
2027	else
2028	other = rme9652->playback_substream;
2029
2030	if (other) {
2031	struct snd_pcm_substream *s;
2032	snd_pcm_group_for_each_entry(s, substream) {
2033	if (s == other) {
2034	snd_pcm_trigger_done(substream: s, master: substream);
2035	if (cmd == SNDRV_PCM_TRIGGER_START)
2036	running |= 1 << s->stream;
2037	else
2038	running &= ~(1 << s->stream);
2039	goto _ok;
2040	}
2041	}
2042	if (cmd == SNDRV_PCM_TRIGGER_START) {
2043	if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
2044	substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2045	rme9652_silence_playback(rme9652);
2046	} else {
2047	if (running &&
2048	substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2049	rme9652_silence_playback(rme9652);
2050	}
2051	} else {
2052	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2053	rme9652_silence_playback(rme9652);
2054	}
2055	_ok:
2056	snd_pcm_trigger_done(substream, master: substream);
2057	if (!rme9652->running && running)
2058	rme9652_start(s: rme9652);
2059	else if (rme9652->running && !running)
2060	rme9652_stop(s: rme9652);
2061	rme9652->running = running;
2062
2063	return 0;
2064	}
2065
2066	static int snd_rme9652_prepare(struct snd_pcm_substream *substream)
2067	{
2068	struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
2069
2070	guard(spinlock_irqsave)(l: &rme9652->lock);
2071	if (!rme9652->running)
2072	rme9652_reset_hw_pointer(rme9652);
2073	return 0;
2074	}
2075
2076	static const struct snd_pcm_hardware snd_rme9652_playback_subinfo =
2077	{
2078	.info = (SNDRV_PCM_INFO_MMAP |
2079	SNDRV_PCM_INFO_MMAP_VALID |
2080	SNDRV_PCM_INFO_NONINTERLEAVED |
2081	SNDRV_PCM_INFO_SYNC_START |
2082	SNDRV_PCM_INFO_DOUBLE),
2083	.formats = SNDRV_PCM_FMTBIT_S32_LE,
2084	.rates = (SNDRV_PCM_RATE_44100 |
2085	SNDRV_PCM_RATE_48000 |
2086	SNDRV_PCM_RATE_88200 |
2087	SNDRV_PCM_RATE_96000),
2088	.rate_min = 44100,
2089	.rate_max = 96000,
2090	.channels_min = 10,
2091	.channels_max = 26,
2092	.buffer_bytes_max = RME9652_CHANNEL_BUFFER_BYTES * 26,
2093	.period_bytes_min = (64 * 4) * 10,
2094	.period_bytes_max = (8192 * 4) * 26,
2095	.periods_min = 2,
2096	.periods_max = 2,
2097	.fifo_size = 0,
2098	};
2099
2100	static const struct snd_pcm_hardware snd_rme9652_capture_subinfo =
2101	{
2102	.info = (SNDRV_PCM_INFO_MMAP |
2103	SNDRV_PCM_INFO_MMAP_VALID |
2104	SNDRV_PCM_INFO_NONINTERLEAVED |
2105	SNDRV_PCM_INFO_SYNC_START),
2106	.formats = SNDRV_PCM_FMTBIT_S32_LE,
2107	.rates = (SNDRV_PCM_RATE_44100 |
2108	SNDRV_PCM_RATE_48000 |
2109	SNDRV_PCM_RATE_88200 |
2110	SNDRV_PCM_RATE_96000),
2111	.rate_min = 44100,
2112	.rate_max = 96000,
2113	.channels_min = 10,
2114	.channels_max = 26,
2115	.buffer_bytes_max = RME9652_CHANNEL_BUFFER_BYTES *26,
2116	.period_bytes_min = (64 * 4) * 10,
2117	.period_bytes_max = (8192 * 4) * 26,
2118	.periods_min = 2,
2119	.periods_max = 2,
2120	.fifo_size = 0,
2121	};
2122
2123	static const unsigned int period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
2124
2125	static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
2126	.count = ARRAY_SIZE(period_sizes),
2127	.list = period_sizes,
2128	.mask = 0
2129	};
2130
2131	static int snd_rme9652_hw_rule_channels(struct snd_pcm_hw_params *params,
2132	struct snd_pcm_hw_rule *rule)
2133	{
2134	struct snd_rme9652 *rme9652 = rule->private;
2135	struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
2136	unsigned int list[2] = { rme9652->ds_channels, rme9652->ss_channels };
2137	return snd_interval_list(i: c, count: 2, list, mask: 0);
2138	}
2139
2140	static int snd_rme9652_hw_rule_channels_rate(struct snd_pcm_hw_params *params,
2141	struct snd_pcm_hw_rule *rule)
2142	{
2143	struct snd_rme9652 *rme9652 = rule->private;
2144	struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
2145	struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
2146	if (r->min > 48000) {
2147	struct snd_interval t = {
2148	.min = rme9652->ds_channels,
2149	.max = rme9652->ds_channels,
2150	.integer = 1,
2151	};
2152	return snd_interval_refine(i: c, v: &t);
2153	} else if (r->max < 88200) {
2154	struct snd_interval t = {
2155	.min = rme9652->ss_channels,
2156	.max = rme9652->ss_channels,
2157	.integer = 1,
2158	};
2159	return snd_interval_refine(i: c, v: &t);
2160	}
2161	return 0;
2162	}
2163
2164	static int snd_rme9652_hw_rule_rate_channels(struct snd_pcm_hw_params *params,
2165	struct snd_pcm_hw_rule *rule)
2166	{
2167	struct snd_rme9652 *rme9652 = rule->private;
2168	struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
2169	struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
2170	if (c->min >= rme9652->ss_channels) {
2171	struct snd_interval t = {
2172	.min = 44100,
2173	.max = 48000,
2174	.integer = 1,
2175	};
2176	return snd_interval_refine(i: r, v: &t);
2177	} else if (c->max <= rme9652->ds_channels) {
2178	struct snd_interval t = {
2179	.min = 88200,
2180	.max = 96000,
2181	.integer = 1,
2182	};
2183	return snd_interval_refine(i: r, v: &t);
2184	}
2185	return 0;
2186	}
2187
2188	static int snd_rme9652_playback_open(struct snd_pcm_substream *substream)
2189	{
2190	struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
2191	struct snd_pcm_runtime *runtime = substream->runtime;
2192
2193	scoped_guard(spinlock_irq, &rme9652->lock) {
2194	snd_pcm_set_sync(substream);
2195
2196	runtime->hw = snd_rme9652_playback_subinfo;
2197	snd_pcm_set_runtime_buffer(substream, bufp: &rme9652->playback_dma_buf);
2198
2199	if (rme9652->capture_substream == NULL) {
2200	rme9652_stop(s: rme9652);
2201	rme9652_set_thru(rme9652, channel: -1, enable: 0);
2202	}
2203
2204	rme9652->playback_pid = current->pid;
2205	rme9652->playback_substream = substream;
2206	}
2207
2208	snd_pcm_hw_constraint_msbits(runtime, cond: 0, width: 32, msbits: 24);
2209	snd_pcm_hw_constraint_list(runtime, cond: 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, l: &hw_constraints_period_sizes);
2210	snd_pcm_hw_rule_add(runtime, cond: 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2211	func: snd_rme9652_hw_rule_channels, private: rme9652,
2212	SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2213	snd_pcm_hw_rule_add(runtime, cond: 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2214	func: snd_rme9652_hw_rule_channels_rate, private: rme9652,
2215	SNDRV_PCM_HW_PARAM_RATE, -1);
2216	snd_pcm_hw_rule_add(runtime, cond: 0, SNDRV_PCM_HW_PARAM_RATE,
2217	func: snd_rme9652_hw_rule_rate_channels, private: rme9652,
2218	SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2219
2220	rme9652->creg_spdif_stream = rme9652->creg_spdif;
2221	rme9652->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
2222	snd_ctl_notify(card: rme9652->card, SNDRV_CTL_EVENT_MASK_VALUE |
2223	SNDRV_CTL_EVENT_MASK_INFO, id: &rme9652->spdif_ctl->id);
2224	return 0;
2225	}
2226
2227	static int snd_rme9652_playback_release(struct snd_pcm_substream *substream)
2228	{
2229	struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
2230
2231	scoped_guard(spinlock_irq, &rme9652->lock) {
2232	rme9652->playback_pid = -1;
2233	rme9652->playback_substream = NULL;
2234	}
2235
2236	rme9652->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
2237	snd_ctl_notify(card: rme9652->card, SNDRV_CTL_EVENT_MASK_VALUE |
2238	SNDRV_CTL_EVENT_MASK_INFO, id: &rme9652->spdif_ctl->id);
2239	return 0;
2240	}
2241
2242
2243	static int snd_rme9652_capture_open(struct snd_pcm_substream *substream)
2244	{
2245	struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
2246	struct snd_pcm_runtime *runtime = substream->runtime;
2247
2248	scoped_guard(spinlock_irq, &rme9652->lock) {
2249	snd_pcm_set_sync(substream);
2250
2251	runtime->hw = snd_rme9652_capture_subinfo;
2252	snd_pcm_set_runtime_buffer(substream, bufp: &rme9652->capture_dma_buf);
2253
2254	if (rme9652->playback_substream == NULL) {
2255	rme9652_stop(s: rme9652);
2256	rme9652_set_thru(rme9652, channel: -1, enable: 0);
2257	}
2258
2259	rme9652->capture_pid = current->pid;
2260	rme9652->capture_substream = substream;
2261	}
2262
2263	snd_pcm_hw_constraint_msbits(runtime, cond: 0, width: 32, msbits: 24);
2264	snd_pcm_hw_constraint_list(runtime, cond: 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, l: &hw_constraints_period_sizes);
2265	snd_pcm_hw_rule_add(runtime, cond: 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2266	func: snd_rme9652_hw_rule_channels, private: rme9652,
2267	SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2268	snd_pcm_hw_rule_add(runtime, cond: 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2269	func: snd_rme9652_hw_rule_channels_rate, private: rme9652,
2270	SNDRV_PCM_HW_PARAM_RATE, -1);
2271	snd_pcm_hw_rule_add(runtime, cond: 0, SNDRV_PCM_HW_PARAM_RATE,
2272	func: snd_rme9652_hw_rule_rate_channels, private: rme9652,
2273	SNDRV_PCM_HW_PARAM_CHANNELS, -1);
2274	return 0;
2275	}
2276
2277	static int snd_rme9652_capture_release(struct snd_pcm_substream *substream)
2278	{
2279	struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);
2280
2281	guard(spinlock_irq)(l: &rme9652->lock);
2282
2283	rme9652->capture_pid = -1;
2284	rme9652->capture_substream = NULL;
2285
2286	return 0;
2287	}
2288
2289	static const struct snd_pcm_ops snd_rme9652_playback_ops = {
2290	.open = snd_rme9652_playback_open,
2291	.close = snd_rme9652_playback_release,
2292	.ioctl = snd_rme9652_ioctl,
2293	.hw_params = snd_rme9652_hw_params,
2294	.prepare = snd_rme9652_prepare,
2295	.trigger = snd_rme9652_trigger,
2296	.pointer = snd_rme9652_hw_pointer,
2297	.copy = snd_rme9652_playback_copy,
2298	.fill_silence = snd_rme9652_hw_silence,
2299	};
2300
2301	static const struct snd_pcm_ops snd_rme9652_capture_ops = {
2302	.open = snd_rme9652_capture_open,
2303	.close = snd_rme9652_capture_release,
2304	.ioctl = snd_rme9652_ioctl,
2305	.hw_params = snd_rme9652_hw_params,
2306	.prepare = snd_rme9652_prepare,
2307	.trigger = snd_rme9652_trigger,
2308	.pointer = snd_rme9652_hw_pointer,
2309	.copy = snd_rme9652_capture_copy,
2310	};
2311
2312	static int snd_rme9652_create_pcm(struct snd_card *card,
2313	struct snd_rme9652 *rme9652)
2314	{
2315	struct snd_pcm *pcm;
2316	int err;
2317
2318	err = snd_pcm_new(card, id: rme9652->card_name, device: 0, playback_count: 1, capture_count: 1, rpcm: &pcm);
2319	if (err < 0)
2320	return err;
2321
2322	rme9652->pcm = pcm;
2323	pcm->private_data = rme9652;
2324	strscpy(pcm->name, rme9652->card_name);
2325
2326	snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_PLAYBACK, ops: &snd_rme9652_playback_ops);
2327	snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_CAPTURE, ops: &snd_rme9652_capture_ops);
2328
2329	pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
2330
2331	return 0;
2332	}
2333
2334	static int snd_rme9652_create(struct snd_card *card,
2335	struct snd_rme9652 *rme9652,
2336	int precise_ptr)
2337	{
2338	struct pci_dev *pci = rme9652->pci;
2339	int err;
2340	int status;
2341	unsigned short rev;
2342
2343	rme9652->irq = -1;
2344	rme9652->card = card;
2345
2346	pci_read_config_word(dev: rme9652->pci, PCI_CLASS_REVISION, val: &rev);
2347
2348	switch (rev & 0xff) {
2349	case 3:
2350	case 4:
2351	case 8:
2352	case 9:
2353	break;
2354
2355	default:
2356	/* who knows? */
2357	return -ENODEV;
2358	}
2359
2360	err = pcim_enable_device(pdev: pci);
2361	if (err < 0)
2362	return err;
2363
2364	spin_lock_init(&rme9652->lock);
2365
2366	err = pcim_request_all_regions(pdev: pci, name: "rme9652");
2367	if (err < 0)
2368	return err;
2369	rme9652->port = pci_resource_start(pci, 0);
2370	rme9652->iobase = devm_ioremap(dev: &pci->dev, offset: rme9652->port, RME9652_IO_EXTENT);
2371	if (rme9652->iobase == NULL) {
2372	dev_err(card->dev, "unable to remap region 0x%lx-0x%lx\n",
2373	rme9652->port, rme9652->port + RME9652_IO_EXTENT - 1);
2374	return -EBUSY;
2375	}
2376
2377	if (devm_request_irq(dev: &pci->dev, irq: pci->irq, handler: snd_rme9652_interrupt,
2378	IRQF_SHARED, KBUILD_MODNAME, dev_id: rme9652)) {
2379	dev_err(card->dev, "unable to request IRQ %d\n", pci->irq);
2380	return -EBUSY;
2381	}
2382	rme9652->irq = pci->irq;
2383	card->sync_irq = rme9652->irq;
2384	rme9652->precise_ptr = precise_ptr;
2385
2386	/* Determine the h/w rev level of the card. This seems like
2387	a particularly kludgy way to encode it, but its what RME
2388	chose to do, so we follow them ...
2389	*/
2390
2391	status = rme9652_read(rme9652, RME9652_status_register);
2392	if (rme9652_decode_spdif_rate(status&RME9652_F) == 1) {
2393	rme9652->hw_rev = 15;
2394	} else {
2395	rme9652->hw_rev = 11;
2396	}
2397
2398	/* Differentiate between the standard Hammerfall, and the
2399	"Light", which does not have the expansion board. This
2400	method comes from information received from Mathhias
2401	Clausen at RME. Display the EEPROM and h/w revID where
2402	relevant.
2403	*/
2404
2405	switch (rev) {
2406	case 8: /* original eprom */
2407	strscpy(card->driver, "RME9636");
2408	if (rme9652->hw_rev == 15) {
2409	rme9652->card_name = "RME Digi9636 (Rev 1.5)";
2410	} else {
2411	rme9652->card_name = "RME Digi9636";
2412	}
2413	rme9652->ss_channels = RME9636_NCHANNELS;
2414	break;
2415	case 9: /* W36_G EPROM */
2416	strscpy(card->driver, "RME9636");
2417	rme9652->card_name = "RME Digi9636 (Rev G)";
2418	rme9652->ss_channels = RME9636_NCHANNELS;
2419	break;
2420	case 4: /* W52_G EPROM */
2421	strscpy(card->driver, "RME9652");
2422	rme9652->card_name = "RME Digi9652 (Rev G)";
2423	rme9652->ss_channels = RME9652_NCHANNELS;
2424	break;
2425	case 3: /* original eprom */
2426	strscpy(card->driver, "RME9652");
2427	if (rme9652->hw_rev == 15) {
2428	rme9652->card_name = "RME Digi9652 (Rev 1.5)";
2429	} else {
2430	rme9652->card_name = "RME Digi9652";
2431	}
2432	rme9652->ss_channels = RME9652_NCHANNELS;
2433	break;
2434	}
2435
2436	rme9652->ds_channels = (rme9652->ss_channels - 2) / 2 + 2;
2437
2438	pci_set_master(dev: rme9652->pci);
2439
2440	err = snd_rme9652_initialize_memory(rme9652);
2441	if (err < 0)
2442	return err;
2443
2444	err = snd_rme9652_create_pcm(card, rme9652);
2445	if (err < 0)
2446	return err;
2447
2448	err = snd_rme9652_create_controls(card, rme9652);
2449	if (err < 0)
2450	return err;
2451
2452	snd_rme9652_proc_init(rme9652);
2453
2454	rme9652->last_spdif_sample_rate = -1;
2455	rme9652->last_adat_sample_rate = -1;
2456	rme9652->playback_pid = -1;
2457	rme9652->capture_pid = -1;
2458	rme9652->capture_substream = NULL;
2459	rme9652->playback_substream = NULL;
2460
2461	snd_rme9652_set_defaults(rme9652);
2462
2463	if (rme9652->hw_rev == 15) {
2464	rme9652_initialize_spdif_receiver (rme9652);
2465	}
2466
2467	return 0;
2468	}
2469
2470	static int snd_rme9652_probe(struct pci_dev *pci,
2471	const struct pci_device_id *pci_id)
2472	{
2473	static int dev;
2474	struct snd_rme9652 *rme9652;
2475	struct snd_card *card;
2476	int err;
2477
2478	if (dev >= SNDRV_CARDS)
2479	return -ENODEV;
2480	if (!enable[dev]) {
2481	dev++;
2482	return -ENOENT;
2483	}
2484
2485	err = snd_devm_card_new(parent: &pci->dev, idx: index[dev], xid: id[dev], THIS_MODULE,
2486	extra_size: sizeof(struct snd_rme9652), card_ret: &card);
2487
2488	if (err < 0)
2489	return err;
2490
2491	rme9652 = (struct snd_rme9652 *) card->private_data;
2492	card->private_free = snd_rme9652_card_free;
2493	rme9652->dev = dev;
2494	rme9652->pci = pci;
2495	err = snd_rme9652_create(card, rme9652, precise_ptr: precise_ptr[dev]);
2496	if (err)
2497	goto error;
2498
2499	strscpy(card->shortname, rme9652->card_name);
2500
2501	sprintf(buf: card->longname, fmt: "%s at 0x%lx, irq %d",
2502	card->shortname, rme9652->port, rme9652->irq);
2503	err = snd_card_register(card);
2504	if (err)
2505	goto error;
2506	pci_set_drvdata(pdev: pci, data: card);
2507	dev++;
2508	return 0;
2509
2510	error:
2511	snd_card_free(card);
2512	return err;
2513	}
2514
2515	static struct pci_driver rme9652_driver = {
2516	.name = KBUILD_MODNAME,
2517	.id_table = snd_rme9652_ids,
2518	.probe = snd_rme9652_probe,
2519	};
2520
2521	module_pci_driver(rme9652_driver);
2522