1	// SPDX-License-Identifier: GPL-2.0-or-later
2	/*
3	* Driver for C-Media CMI8338 and 8738 PCI soundcards.
4	* Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
5	*/
6
7	/* Does not work. Warning may block system in capture mode */
8	/* #define USE_VAR48KRATE */
9
10	#include <linux/io.h>
11	#include <linux/delay.h>
12	#include <linux/interrupt.h>
13	#include <linux/init.h>
14	#include <linux/pci.h>
15	#include <linux/slab.h>
16	#include <linux/gameport.h>
17	#include <linux/module.h>
18	#include <linux/mutex.h>
19	#include <sound/core.h>
20	#include <sound/info.h>
21	#include <sound/control.h>
22	#include <sound/pcm.h>
23	#include <sound/rawmidi.h>
24	#include <sound/mpu401.h>
25	#include <sound/opl3.h>
26	#include <sound/sb.h>
27	#include <sound/asoundef.h>
28	#include <sound/initval.h>
29
30	MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
31	MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
32	MODULE_LICENSE("GPL");
33
34	#if IS_REACHABLE(CONFIG_GAMEPORT)
35	#define SUPPORT_JOYSTICK 1
36	#endif
37
38	static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
39	static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
40	static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
41	static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1};
42	static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
43	static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
44	#ifdef SUPPORT_JOYSTICK
45	static int joystick_port[SNDRV_CARDS];
46	#endif
47
48	module_param_array(index, int, NULL, 0444);
49	MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
50	module_param_array(id, charp, NULL, 0444);
51	MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
52	module_param_array(enable, bool, NULL, 0444);
53	MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
54	module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
55	MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
56	module_param_hw_array(fm_port, long, ioport, NULL, 0444);
57	MODULE_PARM_DESC(fm_port, "FM port.");
58	module_param_array(soft_ac3, bool, NULL, 0444);
59	MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
60	#ifdef SUPPORT_JOYSTICK
61	module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
62	MODULE_PARM_DESC(joystick_port, "Joystick port address.");
63	#endif
64
65	/*
66	* CM8x38 registers definition
67	*/
68
69	#define CM_REG_FUNCTRL0 0x00
70	#define CM_RST_CH1 0x00080000
71	#define CM_RST_CH0 0x00040000
72	#define CM_CHEN1 0x00020000 /* ch1: enable */
73	#define CM_CHEN0 0x00010000 /* ch0: enable */
74	#define CM_PAUSE1 0x00000008 /* ch1: pause */
75	#define CM_PAUSE0 0x00000004 /* ch0: pause */
76	#define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
77	#define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
78
79	#define CM_REG_FUNCTRL1 0x04
80	#define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
81	#define CM_DSFC_SHIFT 13
82	#define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
83	#define CM_ASFC_SHIFT 10
84	#define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
85	#define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
86	#define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
87	#define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
88	#define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
89	#define CM_BREQ 0x00000010 /* bus master enabled */
90	#define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
91	#define CM_UART_EN 0x00000004 /* legacy UART */
92	#define CM_JYSTK_EN 0x00000002 /* legacy joystick */
93	#define CM_ZVPORT 0x00000001 /* ZVPORT */
94
95	#define CM_REG_CHFORMAT 0x08
96
97	#define CM_CHB3D5C 0x80000000 /* 5,6 channels */
98	#define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
99	#define CM_CHB3D 0x20000000 /* 4 channels */
100
101	#define CM_CHIP_MASK1 0x1f000000
102	#define CM_CHIP_037 0x01000000
103	#define CM_SETLAT48 0x00800000 /* set latency timer 48h */
104	#define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
105	#define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
106	#define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
107	#define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
108	#define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
109	/* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
110
111	#define CM_ADCBITLEN_MASK 0x0000C000
112	#define CM_ADCBITLEN_16 0x00000000
113	#define CM_ADCBITLEN_15 0x00004000
114	#define CM_ADCBITLEN_14 0x00008000
115	#define CM_ADCBITLEN_13 0x0000C000
116
117	#define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
118	#define CM_ADCDACLEN_060 0x00000000
119	#define CM_ADCDACLEN_066 0x00001000
120	#define CM_ADCDACLEN_130 0x00002000
121	#define CM_ADCDACLEN_280 0x00003000
122
123	#define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
124	#define CM_ADCDLEN_ORIGINAL 0x00000000
125	#define CM_ADCDLEN_EXTRA 0x00001000
126	#define CM_ADCDLEN_24K 0x00002000
127	#define CM_ADCDLEN_WEIGHT 0x00003000
128
129	#define CM_CH1_SRATE_176K 0x00000800
130	#define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
131	#define CM_CH1_SRATE_88K 0x00000400
132	#define CM_CH0_SRATE_176K 0x00000200
133	#define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
134	#define CM_CH0_SRATE_88K 0x00000100
135	#define CM_CH0_SRATE_128K 0x00000300
136	#define CM_CH0_SRATE_MASK 0x00000300
137
138	#define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
139	#define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
140	#define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
141	#define CM_SPDLOCKED 0x00000010
142
143	#define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
144	#define CM_CH1FMT_SHIFT 2
145	#define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
146	#define CM_CH0FMT_SHIFT 0
147
148	#define CM_REG_INT_HLDCLR 0x0C
149	#define CM_CHIP_MASK2 0xff000000
150	#define CM_CHIP_8768 0x20000000
151	#define CM_CHIP_055 0x08000000
152	#define CM_CHIP_039 0x04000000
153	#define CM_CHIP_039_6CH 0x01000000
154	#define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
155	#define CM_TDMA_INT_EN 0x00040000
156	#define CM_CH1_INT_EN 0x00020000
157	#define CM_CH0_INT_EN 0x00010000
158
159	#define CM_REG_INT_STATUS 0x10
160	#define CM_INTR 0x80000000
161	#define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
162	#define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
163	#define CM_UARTINT 0x00010000
164	#define CM_LTDMAINT 0x00008000
165	#define CM_HTDMAINT 0x00004000
166	#define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
167	#define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
168	#define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
169	#define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
170	#define CM_CH1BUSY 0x00000008
171	#define CM_CH0BUSY 0x00000004
172	#define CM_CHINT1 0x00000002
173	#define CM_CHINT0 0x00000001
174
175	#define CM_REG_LEGACY_CTRL 0x14
176	#define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
177	#define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
178	#define CM_VMPU_330 0x00000000
179	#define CM_VMPU_320 0x20000000
180	#define CM_VMPU_310 0x40000000
181	#define CM_VMPU_300 0x60000000
182	#define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
183	#define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
184	#define CM_VSBSEL_220 0x00000000
185	#define CM_VSBSEL_240 0x04000000
186	#define CM_VSBSEL_260 0x08000000
187	#define CM_VSBSEL_280 0x0C000000
188	#define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
189	#define CM_FMSEL_388 0x00000000
190	#define CM_FMSEL_3C8 0x01000000
191	#define CM_FMSEL_3E0 0x02000000
192	#define CM_FMSEL_3E8 0x03000000
193	#define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
194	#define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
195	#define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
196	#define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
197	#define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
198	#define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
199	#define CM_C_EECS 0x00040000
200	#define CM_C_EEDI46 0x00020000
201	#define CM_C_EECK46 0x00010000
202	#define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
203	#define CM_CENTR2LIN 0x00004000 /* line-in as center out */
204	#define CM_BASE2LIN 0x00002000 /* line-in as bass out */
205	#define CM_EXBASEN 0x00001000 /* external bass input enable */
206
207	#define CM_REG_MISC_CTRL 0x18
208	#define CM_PWD 0x80000000 /* power down */
209	#define CM_RESET 0x40000000
210	#define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
211	#define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
212	#define CM_TXVX 0x08000000 /* model 037? */
213	#define CM_N4SPK3D 0x04000000 /* copy front to rear */
214	#define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
215	#define CM_SPDIF48K 0x01000000 /* write */
216	#define CM_SPATUS48K 0x01000000 /* read */
217	#define CM_ENDBDAC 0x00800000 /* enable double dac */
218	#define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
219	#define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
220	#define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
221	#define CM_FM_EN 0x00080000 /* enable legacy FM */
222	#define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
223	#define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
224	#define CM_VIDWPDSB 0x00010000 /* model 037? */
225	#define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
226	#define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
227	#define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
228	#define CM_VIDWPPRT 0x00002000 /* model 037? */
229	#define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
230	#define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
231	#define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
232	#define CM_ENCENTER 0x00000080
233	#define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
234	#define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
235	#define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
236	#define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
237	#define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
238	#define CM_UPDDMA_2048 0x00000000
239	#define CM_UPDDMA_1024 0x00000004
240	#define CM_UPDDMA_512 0x00000008
241	#define CM_UPDDMA_256 0x0000000C
242	#define CM_TWAIT_MASK 0x00000003 /* model 037 */
243	#define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
244	#define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
245
246	#define CM_REG_TDMA_POSITION 0x1C
247	#define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
248	#define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
249
250	/* byte */
251	#define CM_REG_MIXER0 0x20
252	#define CM_REG_SBVR 0x20 /* write: sb16 version */
253	#define CM_REG_DEV 0x20 /* read: hardware device version */
254
255	#define CM_REG_MIXER21 0x21
256	#define CM_UNKNOWN_21_MASK 0x78 /* ? */
257	#define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
258	#define CM_PROINV 0x02 /* SBPro left/right channel switching */
259	#define CM_X_SB16 0x01 /* SB16 compatible */
260
261	#define CM_REG_SB16_DATA 0x22
262	#define CM_REG_SB16_ADDR 0x23
263
264	#define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
265	#define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
266	#define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
267	#define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
268
269	#define CM_REG_MIXER1 0x24
270	#define CM_FMMUTE 0x80 /* mute FM */
271	#define CM_FMMUTE_SHIFT 7
272	#define CM_WSMUTE 0x40 /* mute PCM */
273	#define CM_WSMUTE_SHIFT 6
274	#define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
275	#define CM_REAR2LIN_SHIFT 5
276	#define CM_REAR2FRONT 0x10 /* exchange rear/front */
277	#define CM_REAR2FRONT_SHIFT 4
278	#define CM_WAVEINL 0x08 /* digital wave rec. left chan */
279	#define CM_WAVEINL_SHIFT 3
280	#define CM_WAVEINR 0x04 /* digical wave rec. right */
281	#define CM_WAVEINR_SHIFT 2
282	#define CM_X3DEN 0x02 /* 3D surround enable */
283	#define CM_X3DEN_SHIFT 1
284	#define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
285	#define CM_CDPLAY_SHIFT 0
286
287	#define CM_REG_MIXER2 0x25
288	#define CM_RAUXREN 0x80 /* AUX right capture */
289	#define CM_RAUXREN_SHIFT 7
290	#define CM_RAUXLEN 0x40 /* AUX left capture */
291	#define CM_RAUXLEN_SHIFT 6
292	#define CM_VAUXRM 0x20 /* AUX right mute */
293	#define CM_VAUXRM_SHIFT 5
294	#define CM_VAUXLM 0x10 /* AUX left mute */
295	#define CM_VAUXLM_SHIFT 4
296	#define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
297	#define CM_VADMIC_SHIFT 1
298	#define CM_MICGAINZ 0x01 /* mic boost */
299	#define CM_MICGAINZ_SHIFT 0
300
301	#define CM_REG_AUX_VOL 0x26
302	#define CM_VAUXL_MASK 0xf0
303	#define CM_VAUXR_MASK 0x0f
304
305	#define CM_REG_MISC 0x27
306	#define CM_UNKNOWN_27_MASK 0xd8 /* ? */
307	#define CM_XGPO1 0x20
308	// #define CM_XGPBIO 0x04
309	#define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
310	#define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
311	#define CM_SPDVALID 0x02 /* spdif input valid check */
312	#define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
313
314	#define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
315	/*
316	* For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
317	* or identical with AC97 codec?
318	*/
319	#define CM_REG_EXTERN_CODEC CM_REG_AC97
320
321	/*
322	* MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
323	*/
324	#define CM_REG_MPU_PCI 0x40
325
326	/*
327	* FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
328	*/
329	#define CM_REG_FM_PCI 0x50
330
331	/*
332	* access from SB-mixer port
333	*/
334	#define CM_REG_EXTENT_IND 0xf0
335	#define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
336	#define CM_VPHONE_SHIFT 5
337	#define CM_VPHOM 0x10 /* Phone mute control */
338	#define CM_VSPKM 0x08 /* Speaker mute control, default high */
339	#define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
340	#define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
341	#define CM_VADMIC3 0x01 /* Mic record boost */
342
343	/*
344	* CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
345	* the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
346	* unit (readonly?).
347	*/
348	#define CM_REG_PLL 0xf8
349
350	/*
351	* extended registers
352	*/
353	#define CM_REG_CH0_FRAME1 0x80 /* write: base address */
354	#define CM_REG_CH0_FRAME2 0x84 /* read: current address */
355	#define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
356	#define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
357
358	#define CM_REG_EXT_MISC 0x90
359	#define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
360	#define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
361	#define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
362	#define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
363	#define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
364	#define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
365	#define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
366	#define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
367
368	/*
369	* size of i/o region
370	*/
371	#define CM_EXTENT_CODEC 0x100
372	#define CM_EXTENT_MIDI 0x2
373	#define CM_EXTENT_SYNTH 0x4
374
375
376	/*
377	* channels for playback / capture
378	*/
379	#define CM_CH_PLAY 0
380	#define CM_CH_CAPT 1
381
382	/*
383	* flags to check device open/close
384	*/
385	#define CM_OPEN_NONE 0
386	#define CM_OPEN_CH_MASK 0x01
387	#define CM_OPEN_DAC 0x10
388	#define CM_OPEN_ADC 0x20
389	#define CM_OPEN_SPDIF 0x40
390	#define CM_OPEN_MCHAN 0x80
391	#define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
392	#define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
393	#define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
394	#define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
395	#define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
396	#define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
397
398
399	#if CM_CH_PLAY == 1
400	#define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
401	#define CM_PLAYBACK_SPDF CM_SPDF_1
402	#define CM_CAPTURE_SPDF CM_SPDF_0
403	#else
404	#define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
405	#define CM_PLAYBACK_SPDF CM_SPDF_0
406	#define CM_CAPTURE_SPDF CM_SPDF_1
407	#endif
408
409
410	/*
411	* driver data
412	*/
413
414	struct cmipci_pcm {
415	struct snd_pcm_substream *substream;
416	u8 running; /* dac/adc running? */
417	u8 fmt; /* format bits */
418	u8 is_dac;
419	u8 needs_silencing;
420	unsigned int dma_size; /* in frames */
421	unsigned int shift;
422	unsigned int ch; /* channel (0/1) */
423	unsigned int offset; /* physical address of the buffer */
424	};
425
426	/* mixer elements toggled/resumed during ac3 playback */
427	struct cmipci_mixer_auto_switches {
428	const char *name; /* switch to toggle */
429	int toggle_on; /* value to change when ac3 mode */
430	};
431	static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
432	{"PCM Playback Switch", 0},
433	{"IEC958 Output Switch", 1},
434	{"IEC958 Mix Analog", 0},
435	// {"IEC958 Out To DAC", 1}, // no longer used
436	{"IEC958 Loop", 0},
437	};
438	#define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
439
440	struct cmipci {
441	struct snd_card *card;
442
443	struct pci_dev *pci;
444	unsigned int device; /* device ID */
445	int irq;
446
447	unsigned long iobase;
448	unsigned int ctrl; /* FUNCTRL0 current value */
449
450	struct snd_pcm *pcm; /* DAC/ADC PCM */
451	struct snd_pcm *pcm2; /* 2nd DAC */
452	struct snd_pcm *pcm_spdif; /* SPDIF */
453
454	int chip_version;
455	int max_channels;
456	unsigned int can_ac3_sw: 1;
457	unsigned int can_ac3_hw: 1;
458	unsigned int can_multi_ch: 1;
459	unsigned int can_96k: 1; /* samplerate above 48k */
460	unsigned int do_soft_ac3: 1;
461
462	unsigned int spdif_playback_avail: 1; /* spdif ready? */
463	unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
464	int spdif_counter; /* for software AC3 */
465
466	unsigned int dig_status;
467	unsigned int dig_pcm_status;
468
469	struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
470
471	int opened[2]; /* open mode */
472	struct mutex open_mutex;
473
474	unsigned int mixer_insensitive: 1;
475	struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
476	int mixer_res_status[CM_SAVED_MIXERS];
477
478	struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
479
480	/* external MIDI */
481	struct snd_rawmidi *rmidi;
482
483	#ifdef SUPPORT_JOYSTICK
484	struct gameport *gameport;
485	#endif
486
487	spinlock_t reg_lock;
488
489	unsigned int saved_regs[0x20];
490	unsigned char saved_mixers[0x20];
491	};
492
493
494	/* read/write operations for dword register */
495	static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
496	{
497	outl(value: data, port: cm->iobase + cmd);
498	}
499
500	static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
501	{
502	return inl(port: cm->iobase + cmd);
503	}
504
505	/* read/write operations for word register */
506	static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
507	{
508	outw(value: data, port: cm->iobase + cmd);
509	}
510
511	static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
512	{
513	return inw(port: cm->iobase + cmd);
514	}
515
516	/* read/write operations for byte register */
517	static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
518	{
519	outb(value: data, port: cm->iobase + cmd);
520	}
521
522	static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
523	{
524	return inb(port: cm->iobase + cmd);
525	}
526
527	/* bit operations for dword register */
528	static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
529	{
530	unsigned int val, oval;
531	val = oval = inl(port: cm->iobase + cmd);
532	val |= flag;
533	if (val == oval)
534	return 0;
535	outl(value: val, port: cm->iobase + cmd);
536	return 1;
537	}
538
539	static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
540	{
541	unsigned int val, oval;
542	val = oval = inl(port: cm->iobase + cmd);
543	val &= ~flag;
544	if (val == oval)
545	return 0;
546	outl(value: val, port: cm->iobase + cmd);
547	return 1;
548	}
549
550	/* bit operations for byte register */
551	static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
552	{
553	unsigned char val, oval;
554	val = oval = inb(port: cm->iobase + cmd);
555	val |= flag;
556	if (val == oval)
557	return 0;
558	outb(value: val, port: cm->iobase + cmd);
559	return 1;
560	}
561
562	static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
563	{
564	unsigned char val, oval;
565	val = oval = inb(port: cm->iobase + cmd);
566	val &= ~flag;
567	if (val == oval)
568	return 0;
569	outb(value: val, port: cm->iobase + cmd);
570	return 1;
571	}
572
573
574	/*
575	* PCM interface
576	*/
577
578	/*
579	* calculate frequency
580	*/
581
582	static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
583
584	static unsigned int snd_cmipci_rate_freq(unsigned int rate)
585	{
586	unsigned int i;
587
588	for (i = 0; i < ARRAY_SIZE(rates); i++) {
589	if (rates[i] == rate)
590	return i;
591	}
592	snd_BUG();
593	return 0;
594	}
595
596	#ifdef USE_VAR48KRATE
597	/*
598	* Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
599	* does it this way .. maybe not. Never get any information from C-Media about
600	* that <werner@suse.de>.
601	*/
602	static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
603	{
604	unsigned int delta, tolerance;
605	int xm, xn, xr;
606
607	for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
608	rate <<= 1;
609	*n = -1;
610	if (*r > 0xff)
611	goto out;
612	tolerance = rate*CM_TOLERANCE_RATE;
613
614	for (xn = (1+2); xn < (0x1f+2); xn++) {
615	for (xm = (1+2); xm < (0xff+2); xm++) {
616	xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
617
618	if (xr < rate)
619	delta = rate - xr;
620	else
621	delta = xr - rate;
622
623	/*
624	* If we found one, remember this,
625	* and try to find a closer one
626	*/
627	if (delta < tolerance) {
628	tolerance = delta;
629	*m = xm - 2;
630	*n = xn - 2;
631	}
632	}
633	}
634	out:
635	return (*n > -1);
636	}
637
638	/*
639	* Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
640	* are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
641	* at the register CM_REG_FUNCTRL1 (0x04).
642	* Problem: other ways are also possible (any information about that?)
643	*/
644	static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
645	{
646	unsigned int reg = CM_REG_PLL + slot;
647	/*
648	* Guess that this programs at reg. 0x04 the pos 15:13/12:10
649	* for DSFC/ASFC (000 up to 111).
650	*/
651
652	/* FIXME: Init (Do we've to set an other register first before programming?) */
653
654	/* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
655	snd_cmipci_write_b(cm, reg, rate>>8);
656	snd_cmipci_write_b(cm, reg, rate&0xff);
657
658	/* FIXME: Setup (Do we've to set an other register first to enable this?) */
659	}
660	#endif /* USE_VAR48KRATE */
661
662	static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
663	struct snd_pcm_hw_params *hw_params)
664	{
665	struct cmipci *cm = snd_pcm_substream_chip(substream);
666	if (params_channels(p: hw_params) > 2) {
667	guard(mutex)(T: &cm->open_mutex);
668	if (cm->opened[CM_CH_PLAY])
669	return -EBUSY;
670	/* reserve the channel A */
671	cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
672	}
673	return 0;
674	}
675
676	static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
677	{
678	int reset = CM_RST_CH0 << (cm->channel[ch].ch);
679	snd_cmipci_write(cm, CM_REG_FUNCTRL0, data: cm->ctrl | reset);
680	snd_cmipci_write(cm, CM_REG_FUNCTRL0, data: cm->ctrl & ~reset);
681	udelay(usec: 10);
682	}
683
684
685	/*
686	*/
687
688	static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
689	static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
690	.count = 3,
691	.list = hw_channels,
692	.mask = 0,
693	};
694	static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
695	.count = 4,
696	.list = hw_channels,
697	.mask = 0,
698	};
699	static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
700	.count = 5,
701	.list = hw_channels,
702	.mask = 0,
703	};
704
705	static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
706	{
707	if (channels > 2) {
708	if (!cm->can_multi_ch || !rec->ch)
709	return -EINVAL;
710	if (rec->fmt != 0x03) /* stereo 16bit only */
711	return -EINVAL;
712	}
713
714	if (cm->can_multi_ch) {
715	guard(spinlock_irq)(l: &cm->reg_lock);
716	if (channels > 2) {
717	snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
718	snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
719	} else {
720	snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
721	snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
722	}
723	if (channels == 8)
724	snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
725	else
726	snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
727	if (channels == 6) {
728	snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
729	snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
730	} else {
731	snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
732	snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
733	}
734	if (channels == 4)
735	snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
736	else
737	snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
738	}
739	return 0;
740	}
741
742
743	/*
744	* prepare playback/capture channel
745	* channel to be used must have been set in rec->ch.
746	*/
747	static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
748	struct snd_pcm_substream *substream)
749	{
750	unsigned int reg, freq, freq_ext, val;
751	unsigned int period_size;
752	struct snd_pcm_runtime *runtime = substream->runtime;
753
754	rec->fmt = 0;
755	rec->shift = 0;
756	if (snd_pcm_format_width(format: runtime->format) >= 16) {
757	rec->fmt |= 0x02;
758	if (snd_pcm_format_width(format: runtime->format) > 16)
759	rec->shift++; /* 24/32bit */
760	}
761	if (runtime->channels > 1)
762	rec->fmt |= 0x01;
763	if (rec->is_dac && set_dac_channels(cm, rec, channels: runtime->channels) < 0) {
764	dev_dbg(cm->card->dev, "cannot set dac channels\n");
765	return -EINVAL;
766	}
767
768	rec->offset = runtime->dma_addr;
769	/* buffer and period sizes in frame */
770	rec->dma_size = runtime->buffer_size << rec->shift;
771	period_size = runtime->period_size << rec->shift;
772	if (runtime->channels > 2) {
773	/* multi-channels */
774	rec->dma_size = (rec->dma_size * runtime->channels) / 2;
775	period_size = (period_size * runtime->channels) / 2;
776	}
777
778	guard(spinlock_irq)(l: &cm->reg_lock);
779
780	/* set buffer address */
781	reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
782	snd_cmipci_write(cm, cmd: reg, data: rec->offset);
783	/* program sample counts */
784	reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
785	snd_cmipci_write_w(cm, cmd: reg, data: rec->dma_size - 1);
786	snd_cmipci_write_w(cm, cmd: reg + 2, data: period_size - 1);
787
788	/* set adc/dac flag */
789	val = rec->ch ? CM_CHADC1 : CM_CHADC0;
790	if (rec->is_dac)
791	cm->ctrl &= ~val;
792	else
793	cm->ctrl |= val;
794	snd_cmipci_write(cm, CM_REG_FUNCTRL0, data: cm->ctrl);
795	/* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
796
797	/* set sample rate */
798	freq = 0;
799	freq_ext = 0;
800	if (runtime->rate > 48000)
801	switch (runtime->rate) {
802	case 88200: freq_ext = CM_CH0_SRATE_88K; break;
803	case 96000: freq_ext = CM_CH0_SRATE_96K; break;
804	case 128000: freq_ext = CM_CH0_SRATE_128K; break;
805	default: snd_BUG(); break;
806	}
807	else
808	freq = snd_cmipci_rate_freq(rate: runtime->rate);
809	val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
810	if (rec->ch) {
811	val &= ~CM_DSFC_MASK;
812	val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
813	} else {
814	val &= ~CM_ASFC_MASK;
815	val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
816	}
817	snd_cmipci_write(cm, CM_REG_FUNCTRL1, data: val);
818	dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
819
820	/* set format */
821	val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
822	if (rec->ch) {
823	val &= ~CM_CH1FMT_MASK;
824	val |= rec->fmt << CM_CH1FMT_SHIFT;
825	} else {
826	val &= ~CM_CH0FMT_MASK;
827	val |= rec->fmt << CM_CH0FMT_SHIFT;
828	}
829	if (cm->can_96k) {
830	val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
831	val |= freq_ext << (rec->ch * 2);
832	}
833	snd_cmipci_write(cm, CM_REG_CHFORMAT, data: val);
834	dev_dbg(cm->card->dev, "chformat = %08x\n", val);
835
836	if (!rec->is_dac && cm->chip_version) {
837	if (runtime->rate > 44100)
838	snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
839	else
840	snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
841	}
842
843	rec->running = 0;
844
845	return 0;
846	}
847
848	/*
849	* PCM trigger/stop
850	*/
851	static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
852	int cmd)
853	{
854	unsigned int inthld, chen, reset, pause;
855
856	inthld = CM_CH0_INT_EN << rec->ch;
857	chen = CM_CHEN0 << rec->ch;
858	reset = CM_RST_CH0 << rec->ch;
859	pause = CM_PAUSE0 << rec->ch;
860
861	guard(spinlock)(l: &cm->reg_lock);
862	switch (cmd) {
863	case SNDRV_PCM_TRIGGER_START:
864	rec->running = 1;
865	/* set interrupt */
866	snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, flag: inthld);
867	cm->ctrl |= chen;
868	/* enable channel */
869	snd_cmipci_write(cm, CM_REG_FUNCTRL0, data: cm->ctrl);
870	dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
871	break;
872	case SNDRV_PCM_TRIGGER_STOP:
873	rec->running = 0;
874	/* disable interrupt */
875	snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, flag: inthld);
876	/* reset */
877	cm->ctrl &= ~chen;
878	snd_cmipci_write(cm, CM_REG_FUNCTRL0, data: cm->ctrl | reset);
879	snd_cmipci_write(cm, CM_REG_FUNCTRL0, data: cm->ctrl & ~reset);
880	rec->needs_silencing = rec->is_dac;
881	break;
882	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
883	case SNDRV_PCM_TRIGGER_SUSPEND:
884	cm->ctrl |= pause;
885	snd_cmipci_write(cm, CM_REG_FUNCTRL0, data: cm->ctrl);
886	break;
887	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
888	case SNDRV_PCM_TRIGGER_RESUME:
889	cm->ctrl &= ~pause;
890	snd_cmipci_write(cm, CM_REG_FUNCTRL0, data: cm->ctrl);
891	break;
892	default:
893	return -EINVAL;
894	}
895	return 0;
896	}
897
898	/*
899	* return the current pointer
900	*/
901	static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
902	struct snd_pcm_substream *substream)
903	{
904	size_t ptr;
905	unsigned int reg, rem, tries;
906
907	if (!rec->running)
908	return 0;
909	#if 1 // this seems better..
910	reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
911	for (tries = 0; tries < 3; tries++) {
912	rem = snd_cmipci_read_w(cm, cmd: reg);
913	if (rem < rec->dma_size)
914	goto ok;
915	}
916	dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
917	return SNDRV_PCM_POS_XRUN;
918	ok:
919	ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
920	#else
921	reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
922	ptr = snd_cmipci_read(cm, reg) - rec->offset;
923	ptr = bytes_to_frames(substream->runtime, ptr);
924	#endif
925	if (substream->runtime->channels > 2)
926	ptr = (ptr * 2) / substream->runtime->channels;
927	return ptr;
928	}
929
930	/*
931	* playback
932	*/
933
934	static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
935	int cmd)
936	{
937	struct cmipci *cm = snd_pcm_substream_chip(substream);
938	return snd_cmipci_pcm_trigger(cm, rec: &cm->channel[CM_CH_PLAY], cmd);
939	}
940
941	static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
942	{
943	struct cmipci *cm = snd_pcm_substream_chip(substream);
944	return snd_cmipci_pcm_pointer(cm, rec: &cm->channel[CM_CH_PLAY], substream);
945	}
946
947
948
949	/*
950	* capture
951	*/
952
953	static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
954	int cmd)
955	{
956	struct cmipci *cm = snd_pcm_substream_chip(substream);
957	return snd_cmipci_pcm_trigger(cm, rec: &cm->channel[CM_CH_CAPT], cmd);
958	}
959
960	static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
961	{
962	struct cmipci *cm = snd_pcm_substream_chip(substream);
963	return snd_cmipci_pcm_pointer(cm, rec: &cm->channel[CM_CH_CAPT], substream);
964	}
965
966
967	/*
968	* hw preparation for spdif
969	*/
970
971	static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
972	struct snd_ctl_elem_info *uinfo)
973	{
974	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
975	uinfo->count = 1;
976	return 0;
977	}
978
979	static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
980	struct snd_ctl_elem_value *ucontrol)
981	{
982	struct cmipci *chip = snd_kcontrol_chip(kcontrol);
983	int i;
984
985	guard(spinlock_irq)(l: &chip->reg_lock);
986	for (i = 0; i < 4; i++)
987	ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
988	return 0;
989	}
990
991	static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
992	struct snd_ctl_elem_value *ucontrol)
993	{
994	struct cmipci *chip = snd_kcontrol_chip(kcontrol);
995	int i, change;
996	unsigned int val;
997
998	val = 0;
999	guard(spinlock_irq)(l: &chip->reg_lock);
1000	for (i = 0; i < 4; i++)
1001	val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1002	change = val != chip->dig_status;
1003	chip->dig_status = val;
1004	return change;
1005	}
1006
1007	static const struct snd_kcontrol_new snd_cmipci_spdif_default =
1008	{
1009	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1010	.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1011	.info = snd_cmipci_spdif_default_info,
1012	.get = snd_cmipci_spdif_default_get,
1013	.put = snd_cmipci_spdif_default_put
1014	};
1015
1016	static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
1017	struct snd_ctl_elem_info *uinfo)
1018	{
1019	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1020	uinfo->count = 1;
1021	return 0;
1022	}
1023
1024	static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
1025	struct snd_ctl_elem_value *ucontrol)
1026	{
1027	ucontrol->value.iec958.status[0] = 0xff;
1028	ucontrol->value.iec958.status[1] = 0xff;
1029	ucontrol->value.iec958.status[2] = 0xff;
1030	ucontrol->value.iec958.status[3] = 0xff;
1031	return 0;
1032	}
1033
1034	static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
1035	{
1036	.access = SNDRV_CTL_ELEM_ACCESS_READ,
1037	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1038	.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
1039	.info = snd_cmipci_spdif_mask_info,
1040	.get = snd_cmipci_spdif_mask_get,
1041	};
1042
1043	static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
1044	struct snd_ctl_elem_info *uinfo)
1045	{
1046	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1047	uinfo->count = 1;
1048	return 0;
1049	}
1050
1051	static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
1052	struct snd_ctl_elem_value *ucontrol)
1053	{
1054	struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1055	int i;
1056
1057	guard(spinlock_irq)(l: &chip->reg_lock);
1058	for (i = 0; i < 4; i++)
1059	ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
1060	return 0;
1061	}
1062
1063	static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
1064	struct snd_ctl_elem_value *ucontrol)
1065	{
1066	struct cmipci *chip = snd_kcontrol_chip(kcontrol);
1067	int i, change;
1068	unsigned int val;
1069
1070	val = 0;
1071	guard(spinlock_irq)(l: &chip->reg_lock);
1072	for (i = 0; i < 4; i++)
1073	val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
1074	change = val != chip->dig_pcm_status;
1075	chip->dig_pcm_status = val;
1076	return change;
1077	}
1078
1079	static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
1080	{
1081	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1082	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1083	.name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1084	.info = snd_cmipci_spdif_stream_info,
1085	.get = snd_cmipci_spdif_stream_get,
1086	.put = snd_cmipci_spdif_stream_put
1087	};
1088
1089	/*
1090	*/
1091
1092	/* save mixer setting and mute for AC3 playback */
1093	static int save_mixer_state(struct cmipci *cm)
1094	{
1095	if (! cm->mixer_insensitive) {
1096	struct snd_ctl_elem_value *val;
1097	unsigned int i;
1098
1099	val = kmalloc(sizeof(*val), GFP_KERNEL);
1100	if (!val)
1101	return -ENOMEM;
1102	for (i = 0; i < CM_SAVED_MIXERS; i++) {
1103	struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1104	if (ctl) {
1105	int event;
1106	memset(val, 0, sizeof(*val));
1107	ctl->get(ctl, val);
1108	cm->mixer_res_status[i] = val->value.integer.value[0];
1109	val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
1110	event = SNDRV_CTL_EVENT_MASK_INFO;
1111	if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
1112	ctl->put(ctl, val); /* toggle */
1113	event |= SNDRV_CTL_EVENT_MASK_VALUE;
1114	}
1115	ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1116	snd_ctl_notify(card: cm->card, mask: event, id: &ctl->id);
1117	}
1118	}
1119	kfree(objp: val);
1120	cm->mixer_insensitive = 1;
1121	}
1122	return 0;
1123	}
1124
1125
1126	/* restore the previously saved mixer status */
1127	static void restore_mixer_state(struct cmipci *cm)
1128	{
1129	if (cm->mixer_insensitive) {
1130	struct snd_ctl_elem_value *val;
1131	unsigned int i;
1132
1133	val = kmalloc(sizeof(*val), GFP_KERNEL);
1134	if (!val)
1135	return;
1136	cm->mixer_insensitive = 0; /* at first clear this;
1137	otherwise the changes will be ignored */
1138	for (i = 0; i < CM_SAVED_MIXERS; i++) {
1139	struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
1140	if (ctl) {
1141	int event;
1142
1143	memset(val, 0, sizeof(*val));
1144	ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1145	ctl->get(ctl, val);
1146	event = SNDRV_CTL_EVENT_MASK_INFO;
1147	if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
1148	val->value.integer.value[0] = cm->mixer_res_status[i];
1149	ctl->put(ctl, val);
1150	event |= SNDRV_CTL_EVENT_MASK_VALUE;
1151	}
1152	snd_ctl_notify(card: cm->card, mask: event, id: &ctl->id);
1153	}
1154	}
1155	kfree(objp: val);
1156	}
1157	}
1158
1159	/* spinlock held! */
1160	static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
1161	{
1162	if (do_ac3) {
1163	/* AC3EN for 037 */
1164	snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1165	/* AC3EN for 039 */
1166	snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1167
1168	if (cm->can_ac3_hw) {
1169	/* SPD24SEL for 037, 0x02 */
1170	/* SPD24SEL for 039, 0x20, but cannot be set */
1171	snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1172	snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1173	} else { /* can_ac3_sw */
1174	/* SPD32SEL for 037 & 039, 0x20 */
1175	snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1176	/* set 176K sample rate to fix 033 HW bug */
1177	if (cm->chip_version == 33) {
1178	if (rate >= 48000) {
1179	snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1180	} else {
1181	snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1182	}
1183	}
1184	}
1185
1186	} else {
1187	snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
1188	snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
1189
1190	if (cm->can_ac3_hw) {
1191	/* chip model >= 37 */
1192	if (snd_pcm_format_width(format: subs->runtime->format) > 16) {
1193	snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1194	snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1195	} else {
1196	snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1197	snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1198	}
1199	} else {
1200	snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1201	snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
1202	snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
1203	}
1204	}
1205	}
1206
1207	static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
1208	{
1209	int rate, err;
1210
1211	rate = subs->runtime->rate;
1212
1213	if (up && do_ac3) {
1214	err = save_mixer_state(cm);
1215	if (err < 0)
1216	return err;
1217	}
1218
1219	guard(spinlock_irq)(l: &cm->reg_lock);
1220	cm->spdif_playback_avail = up;
1221	if (up) {
1222	/* they are controlled via "IEC958 Output Switch" */
1223	/* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1224	/* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1225	if (cm->spdif_playback_enabled)
1226	snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1227	setup_ac3(cm, subs, do_ac3, rate);
1228
1229	if (rate == 48000 || rate == 96000)
1230	snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1231	else
1232	snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
1233	if (rate > 48000)
1234	snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1235	else
1236	snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1237	} else {
1238	/* they are controlled via "IEC958 Output Switch" */
1239	/* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1240	/* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1241	snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1242	snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
1243	setup_ac3(cm, subs, do_ac3: 0, rate: 0);
1244	}
1245	return 0;
1246	}
1247
1248
1249	/*
1250	* preparation
1251	*/
1252
1253	/* playback - enable spdif only on the certain condition */
1254	static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
1255	{
1256	struct cmipci *cm = snd_pcm_substream_chip(substream);
1257	int rate = substream->runtime->rate;
1258	int err, do_spdif, do_ac3 = 0;
1259
1260	do_spdif = (rate >= 44100 && rate <= 96000 &&
1261	substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
1262	substream->runtime->channels == 2);
1263	if (do_spdif && cm->can_ac3_hw)
1264	do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1265	err = setup_spdif_playback(cm, subs: substream, up: do_spdif, do_ac3);
1266	if (err < 0)
1267	return err;
1268	return snd_cmipci_pcm_prepare(cm, rec: &cm->channel[CM_CH_PLAY], substream);
1269	}
1270
1271	/* playback (via device #2) - enable spdif always */
1272	static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
1273	{
1274	struct cmipci *cm = snd_pcm_substream_chip(substream);
1275	int err, do_ac3;
1276
1277	if (cm->can_ac3_hw)
1278	do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
1279	else
1280	do_ac3 = 1; /* doesn't matter */
1281	err = setup_spdif_playback(cm, subs: substream, up: 1, do_ac3);
1282	if (err < 0)
1283	return err;
1284	return snd_cmipci_pcm_prepare(cm, rec: &cm->channel[CM_CH_PLAY], substream);
1285	}
1286
1287	/*
1288	* Apparently, the samples last played on channel A stay in some buffer, even
1289	* after the channel is reset, and get added to the data for the rear DACs when
1290	* playing a multichannel stream on channel B. This is likely to generate
1291	* wraparounds and thus distortions.
1292	* To avoid this, we play at least one zero sample after the actual stream has
1293	* stopped.
1294	*/
1295	static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
1296	{
1297	struct snd_pcm_runtime *runtime = rec->substream->runtime;
1298	unsigned int reg, val;
1299
1300	if (rec->needs_silencing && runtime && runtime->dma_area) {
1301	/* set up a small silence buffer */
1302	memset(runtime->dma_area, 0, PAGE_SIZE);
1303	reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
1304	val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
1305	snd_cmipci_write(cm, cmd: reg, data: val);
1306
1307	/* configure for 16 bits, 2 channels, 8 kHz */
1308	if (runtime->channels > 2)
1309	set_dac_channels(cm, rec, channels: 2);
1310	scoped_guard(spinlock_irq, &cm->reg_lock) {
1311	val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
1312	val &= ~(CM_ASFC_MASK << (rec->ch * 3));
1313	val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
1314	snd_cmipci_write(cm, CM_REG_FUNCTRL1, data: val);
1315	val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
1316	val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
1317	val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
1318	if (cm->can_96k)
1319	val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
1320	snd_cmipci_write(cm, CM_REG_CHFORMAT, data: val);
1321
1322	/* start stream (we don't need interrupts) */
1323	cm->ctrl |= CM_CHEN0 << rec->ch;
1324	snd_cmipci_write(cm, CM_REG_FUNCTRL0, data: cm->ctrl);
1325	}
1326
1327	msleep(msecs: 1);
1328
1329	/* stop and reset stream */
1330	scoped_guard(spinlock_irq, &cm->reg_lock) {
1331	cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1332	val = CM_RST_CH0 << rec->ch;
1333	snd_cmipci_write(cm, CM_REG_FUNCTRL0, data: cm->ctrl | val);
1334	snd_cmipci_write(cm, CM_REG_FUNCTRL0, data: cm->ctrl & ~val);
1335	}
1336
1337	rec->needs_silencing = 0;
1338	}
1339	}
1340
1341	static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
1342	{
1343	struct cmipci *cm = snd_pcm_substream_chip(substream);
1344	setup_spdif_playback(cm, subs: substream, up: 0, do_ac3: 0);
1345	restore_mixer_state(cm);
1346	snd_cmipci_silence_hack(cm, rec: &cm->channel[0]);
1347	return 0;
1348	}
1349
1350	static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
1351	{
1352	struct cmipci *cm = snd_pcm_substream_chip(substream);
1353	snd_cmipci_silence_hack(cm, rec: &cm->channel[1]);
1354	return 0;
1355	}
1356
1357	/* capture */
1358	static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
1359	{
1360	struct cmipci *cm = snd_pcm_substream_chip(substream);
1361	return snd_cmipci_pcm_prepare(cm, rec: &cm->channel[CM_CH_CAPT], substream);
1362	}
1363
1364	/* capture with spdif (via device #2) */
1365	static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
1366	{
1367	struct cmipci *cm = snd_pcm_substream_chip(substream);
1368
1369	scoped_guard(spinlock_irq, &cm->reg_lock) {
1370	snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1371	if (cm->can_96k) {
1372	if (substream->runtime->rate > 48000)
1373	snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1374	else
1375	snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
1376	}
1377	if (snd_pcm_format_width(format: substream->runtime->format) > 16)
1378	snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1379	else
1380	snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1381	}
1382
1383	return snd_cmipci_pcm_prepare(cm, rec: &cm->channel[CM_CH_CAPT], substream);
1384	}
1385
1386	static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
1387	{
1388	struct cmipci *cm = snd_pcm_substream_chip(subs);
1389
1390	guard(spinlock_irq)(l: &cm->reg_lock);
1391	snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
1392	snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
1393
1394	return 0;
1395	}
1396
1397
1398	/*
1399	* interrupt handler
1400	*/
1401	static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
1402	{
1403	struct cmipci *cm = dev_id;
1404	unsigned int status, mask = 0;
1405
1406	/* fastpath out, to ease interrupt sharing */
1407	status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
1408	if (!(status & CM_INTR))
1409	return IRQ_NONE;
1410
1411	/* acknowledge interrupt */
1412	scoped_guard(spinlock, &cm->reg_lock) {
1413	if (status & CM_CHINT0)
1414	mask |= CM_CH0_INT_EN;
1415	if (status & CM_CHINT1)
1416	mask |= CM_CH1_INT_EN;
1417	snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, flag: mask);
1418	snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, flag: mask);
1419	}
1420
1421	if (cm->rmidi && (status & CM_UARTINT))
1422	snd_mpu401_uart_interrupt(irq, dev_id: cm->rmidi->private_data);
1423
1424	if (cm->pcm) {
1425	if ((status & CM_CHINT0) && cm->channel[0].running)
1426	snd_pcm_period_elapsed(substream: cm->channel[0].substream);
1427	if ((status & CM_CHINT1) && cm->channel[1].running)
1428	snd_pcm_period_elapsed(substream: cm->channel[1].substream);
1429	}
1430	return IRQ_HANDLED;
1431	}
1432
1433	/*
1434	* h/w infos
1435	*/
1436
1437	/* playback on channel A */
1438	static const struct snd_pcm_hardware snd_cmipci_playback =
1439	{
1440	.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1441	SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1442	SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1443	.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1444	.rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1445	.rate_min = 5512,
1446	.rate_max = 48000,
1447	.channels_min = 1,
1448	.channels_max = 2,
1449	.buffer_bytes_max = (128*1024),
1450	.period_bytes_min = 64,
1451	.period_bytes_max = (128*1024),
1452	.periods_min = 2,
1453	.periods_max = 1024,
1454	.fifo_size = 0,
1455	};
1456
1457	/* capture on channel B */
1458	static const struct snd_pcm_hardware snd_cmipci_capture =
1459	{
1460	.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1461	SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1462	SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1463	.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1464	.rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1465	.rate_min = 5512,
1466	.rate_max = 48000,
1467	.channels_min = 1,
1468	.channels_max = 2,
1469	.buffer_bytes_max = (128*1024),
1470	.period_bytes_min = 64,
1471	.period_bytes_max = (128*1024),
1472	.periods_min = 2,
1473	.periods_max = 1024,
1474	.fifo_size = 0,
1475	};
1476
1477	/* playback on channel B - stereo 16bit only? */
1478	static const struct snd_pcm_hardware snd_cmipci_playback2 =
1479	{
1480	.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1481	SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1482	SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1483	.formats = SNDRV_PCM_FMTBIT_S16_LE,
1484	.rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
1485	.rate_min = 5512,
1486	.rate_max = 48000,
1487	.channels_min = 2,
1488	.channels_max = 2,
1489	.buffer_bytes_max = (128*1024),
1490	.period_bytes_min = 64,
1491	.period_bytes_max = (128*1024),
1492	.periods_min = 2,
1493	.periods_max = 1024,
1494	.fifo_size = 0,
1495	};
1496
1497	/* spdif playback on channel A */
1498	static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
1499	{
1500	.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1501	SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1502	SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1503	.formats = SNDRV_PCM_FMTBIT_S16_LE,
1504	.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1505	.rate_min = 44100,
1506	.rate_max = 48000,
1507	.channels_min = 2,
1508	.channels_max = 2,
1509	.buffer_bytes_max = (128*1024),
1510	.period_bytes_min = 64,
1511	.period_bytes_max = (128*1024),
1512	.periods_min = 2,
1513	.periods_max = 1024,
1514	.fifo_size = 0,
1515	};
1516
1517	/* spdif playback on channel A (32bit, IEC958 subframes) */
1518	static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
1519	{
1520	.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1521	SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1522	SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1523	.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1524	.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1525	.rate_min = 44100,
1526	.rate_max = 48000,
1527	.channels_min = 2,
1528	.channels_max = 2,
1529	.buffer_bytes_max = (128*1024),
1530	.period_bytes_min = 64,
1531	.period_bytes_max = (128*1024),
1532	.periods_min = 2,
1533	.periods_max = 1024,
1534	.fifo_size = 0,
1535	};
1536
1537	/* spdif capture on channel B */
1538	static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
1539	{
1540	.info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1541	SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
1542	SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
1543	.formats = SNDRV_PCM_FMTBIT_S16_LE |
1544	SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1545	.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1546	.rate_min = 44100,
1547	.rate_max = 48000,
1548	.channels_min = 2,
1549	.channels_max = 2,
1550	.buffer_bytes_max = (128*1024),
1551	.period_bytes_min = 64,
1552	.period_bytes_max = (128*1024),
1553	.periods_min = 2,
1554	.periods_max = 1024,
1555	.fifo_size = 0,
1556	};
1557
1558	/*
1559	* check device open/close
1560	*/
1561	static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
1562	{
1563	int ch = mode & CM_OPEN_CH_MASK;
1564
1565	/* FIXME: a file should wait until the device becomes free
1566	* when it's opened on blocking mode. however, since the current
1567	* pcm framework doesn't pass file pointer before actually opened,
1568	* we can't know whether blocking mode or not in open callback..
1569	*/
1570	guard(mutex)(T: &cm->open_mutex);
1571	if (cm->opened[ch])
1572	return -EBUSY;
1573	cm->opened[ch] = mode;
1574	cm->channel[ch].substream = subs;
1575	if (! (mode & CM_OPEN_DAC)) {
1576	/* disable dual DAC mode */
1577	cm->channel[ch].is_dac = 0;
1578	guard(spinlock_irq)(l: &cm->reg_lock);
1579	snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1580	}
1581	return 0;
1582	}
1583
1584	static void close_device_check(struct cmipci *cm, int mode)
1585	{
1586	int ch = mode & CM_OPEN_CH_MASK;
1587
1588	guard(mutex)(T: &cm->open_mutex);
1589	if (cm->opened[ch] == mode) {
1590	if (cm->channel[ch].substream) {
1591	snd_cmipci_ch_reset(cm, ch);
1592	cm->channel[ch].running = 0;
1593	cm->channel[ch].substream = NULL;
1594	}
1595	cm->opened[ch] = 0;
1596	if (! cm->channel[ch].is_dac) {
1597	/* enable dual DAC mode again */
1598	cm->channel[ch].is_dac = 1;
1599	guard(spinlock_irq)(l: &cm->reg_lock);
1600	snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
1601	}
1602	}
1603	}
1604
1605	/*
1606	*/
1607
1608	static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
1609	{
1610	struct cmipci *cm = snd_pcm_substream_chip(substream);
1611	struct snd_pcm_runtime *runtime = substream->runtime;
1612	int err;
1613
1614	err = open_device_check(cm, CM_OPEN_PLAYBACK, subs: substream);
1615	if (err < 0)
1616	return err;
1617	runtime->hw = snd_cmipci_playback;
1618	if (cm->chip_version == 68) {
1619	runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1620	SNDRV_PCM_RATE_96000;
1621	runtime->hw.rate_max = 96000;
1622	} else if (cm->chip_version == 55) {
1623	runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1624	SNDRV_PCM_RATE_96000 |
1625	SNDRV_PCM_RATE_128000;
1626	runtime->hw.rate_max = 128000;
1627	}
1628	snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, min: 0, max: 0x10000);
1629	cm->dig_pcm_status = cm->dig_status;
1630	return 0;
1631	}
1632
1633	static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
1634	{
1635	struct cmipci *cm = snd_pcm_substream_chip(substream);
1636	struct snd_pcm_runtime *runtime = substream->runtime;
1637	int err;
1638
1639	err = open_device_check(cm, CM_OPEN_CAPTURE, subs: substream);
1640	if (err < 0)
1641	return err;
1642	runtime->hw = snd_cmipci_capture;
1643	if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
1644	runtime->hw.rate_min = 41000;
1645	runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
1646	} else if (cm->chip_version == 55) {
1647	runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1648	SNDRV_PCM_RATE_96000 |
1649	SNDRV_PCM_RATE_128000;
1650	runtime->hw.rate_max = 128000;
1651	}
1652	snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, min: 0, max: 0x10000);
1653	return 0;
1654	}
1655
1656	static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
1657	{
1658	struct cmipci *cm = snd_pcm_substream_chip(substream);
1659	struct snd_pcm_runtime *runtime = substream->runtime;
1660	int err;
1661
1662	/* use channel B */
1663	err = open_device_check(cm, CM_OPEN_PLAYBACK2, subs: substream);
1664	if (err < 0)
1665	return err;
1666	runtime->hw = snd_cmipci_playback2;
1667	guard(mutex)(T: &cm->open_mutex);
1668	if (! cm->opened[CM_CH_PLAY]) {
1669	if (cm->can_multi_ch) {
1670	runtime->hw.channels_max = cm->max_channels;
1671	if (cm->max_channels == 4)
1672	snd_pcm_hw_constraint_list(runtime, cond: 0, SNDRV_PCM_HW_PARAM_CHANNELS, l: &hw_constraints_channels_4);
1673	else if (cm->max_channels == 6)
1674	snd_pcm_hw_constraint_list(runtime, cond: 0, SNDRV_PCM_HW_PARAM_CHANNELS, l: &hw_constraints_channels_6);
1675	else if (cm->max_channels == 8)
1676	snd_pcm_hw_constraint_list(runtime, cond: 0, SNDRV_PCM_HW_PARAM_CHANNELS, l: &hw_constraints_channels_8);
1677	}
1678	}
1679	if (cm->chip_version == 68) {
1680	runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1681	SNDRV_PCM_RATE_96000;
1682	runtime->hw.rate_max = 96000;
1683	} else if (cm->chip_version == 55) {
1684	runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1685	SNDRV_PCM_RATE_96000 |
1686	SNDRV_PCM_RATE_128000;
1687	runtime->hw.rate_max = 128000;
1688	}
1689	snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, min: 0, max: 0x10000);
1690	return 0;
1691	}
1692
1693	static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
1694	{
1695	struct cmipci *cm = snd_pcm_substream_chip(substream);
1696	struct snd_pcm_runtime *runtime = substream->runtime;
1697	int err;
1698
1699	/* use channel A */
1700	err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, subs: substream);
1701	if (err < 0)
1702	return err;
1703	if (cm->can_ac3_hw) {
1704	runtime->hw = snd_cmipci_playback_spdif;
1705	if (cm->chip_version >= 37) {
1706	runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
1707	snd_pcm_hw_constraint_msbits(runtime, cond: 0, width: 32, msbits: 24);
1708	}
1709	if (cm->can_96k) {
1710	runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1711	SNDRV_PCM_RATE_96000;
1712	runtime->hw.rate_max = 96000;
1713	}
1714	} else {
1715	runtime->hw = snd_cmipci_playback_iec958_subframe;
1716	}
1717	snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, min: 0, max: 0x40000);
1718	cm->dig_pcm_status = cm->dig_status;
1719	return 0;
1720	}
1721
1722	static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
1723	{
1724	struct cmipci *cm = snd_pcm_substream_chip(substream);
1725	struct snd_pcm_runtime *runtime = substream->runtime;
1726	int err;
1727
1728	/* use channel B */
1729	err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, subs: substream);
1730	if (err < 0)
1731	return err;
1732	runtime->hw = snd_cmipci_capture_spdif;
1733	if (cm->can_96k && !(cm->chip_version == 68)) {
1734	runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
1735	SNDRV_PCM_RATE_96000;
1736	runtime->hw.rate_max = 96000;
1737	}
1738	snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, min: 0, max: 0x40000);
1739	return 0;
1740	}
1741
1742
1743	/*
1744	*/
1745
1746	static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
1747	{
1748	struct cmipci *cm = snd_pcm_substream_chip(substream);
1749	close_device_check(cm, CM_OPEN_PLAYBACK);
1750	return 0;
1751	}
1752
1753	static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
1754	{
1755	struct cmipci *cm = snd_pcm_substream_chip(substream);
1756	close_device_check(cm, CM_OPEN_CAPTURE);
1757	return 0;
1758	}
1759
1760	static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
1761	{
1762	struct cmipci *cm = snd_pcm_substream_chip(substream);
1763	close_device_check(cm, CM_OPEN_PLAYBACK2);
1764	close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
1765	return 0;
1766	}
1767
1768	static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
1769	{
1770	struct cmipci *cm = snd_pcm_substream_chip(substream);
1771	close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
1772	return 0;
1773	}
1774
1775	static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
1776	{
1777	struct cmipci *cm = snd_pcm_substream_chip(substream);
1778	close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
1779	return 0;
1780	}
1781
1782
1783	/*
1784	*/
1785
1786	static const struct snd_pcm_ops snd_cmipci_playback_ops = {
1787	.open = snd_cmipci_playback_open,
1788	.close = snd_cmipci_playback_close,
1789	.hw_free = snd_cmipci_playback_hw_free,
1790	.prepare = snd_cmipci_playback_prepare,
1791	.trigger = snd_cmipci_playback_trigger,
1792	.pointer = snd_cmipci_playback_pointer,
1793	};
1794
1795	static const struct snd_pcm_ops snd_cmipci_capture_ops = {
1796	.open = snd_cmipci_capture_open,
1797	.close = snd_cmipci_capture_close,
1798	.prepare = snd_cmipci_capture_prepare,
1799	.trigger = snd_cmipci_capture_trigger,
1800	.pointer = snd_cmipci_capture_pointer,
1801	};
1802
1803	static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
1804	.open = snd_cmipci_playback2_open,
1805	.close = snd_cmipci_playback2_close,
1806	.hw_params = snd_cmipci_playback2_hw_params,
1807	.hw_free = snd_cmipci_playback2_hw_free,
1808	.prepare = snd_cmipci_capture_prepare, /* channel B */
1809	.trigger = snd_cmipci_capture_trigger, /* channel B */
1810	.pointer = snd_cmipci_capture_pointer, /* channel B */
1811	};
1812
1813	static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
1814	.open = snd_cmipci_playback_spdif_open,
1815	.close = snd_cmipci_playback_spdif_close,
1816	.hw_free = snd_cmipci_playback_hw_free,
1817	.prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
1818	.trigger = snd_cmipci_playback_trigger,
1819	.pointer = snd_cmipci_playback_pointer,
1820	};
1821
1822	static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
1823	.open = snd_cmipci_capture_spdif_open,
1824	.close = snd_cmipci_capture_spdif_close,
1825	.hw_free = snd_cmipci_capture_spdif_hw_free,
1826	.prepare = snd_cmipci_capture_spdif_prepare,
1827	.trigger = snd_cmipci_capture_trigger,
1828	.pointer = snd_cmipci_capture_pointer,
1829	};
1830
1831
1832	/*
1833	*/
1834
1835	static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
1836	{
1837	struct snd_pcm *pcm;
1838	int err;
1839
1840	err = snd_pcm_new(card: cm->card, id: cm->card->driver, device, playback_count: 1, capture_count: 1, rpcm: &pcm);
1841	if (err < 0)
1842	return err;
1843
1844	snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_PLAYBACK, ops: &snd_cmipci_playback_ops);
1845	snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_CAPTURE, ops: &snd_cmipci_capture_ops);
1846
1847	pcm->private_data = cm;
1848	pcm->info_flags = 0;
1849	strscpy(pcm->name, "C-Media PCI DAC/ADC");
1850	cm->pcm = pcm;
1851
1852	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1853	data: &cm->pci->dev, size: 64*1024, max: 128*1024);
1854
1855	return 0;
1856	}
1857
1858	static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
1859	{
1860	struct snd_pcm *pcm;
1861	int err;
1862
1863	err = snd_pcm_new(card: cm->card, id: cm->card->driver, device, playback_count: 1, capture_count: 0, rpcm: &pcm);
1864	if (err < 0)
1865	return err;
1866
1867	snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_PLAYBACK, ops: &snd_cmipci_playback2_ops);
1868
1869	pcm->private_data = cm;
1870	pcm->info_flags = 0;
1871	strscpy(pcm->name, "C-Media PCI 2nd DAC");
1872	cm->pcm2 = pcm;
1873
1874	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1875	data: &cm->pci->dev, size: 64*1024, max: 128*1024);
1876
1877	return 0;
1878	}
1879
1880	static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
1881	{
1882	struct snd_pcm *pcm;
1883	int err;
1884
1885	err = snd_pcm_new(card: cm->card, id: cm->card->driver, device, playback_count: 1, capture_count: 1, rpcm: &pcm);
1886	if (err < 0)
1887	return err;
1888
1889	snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_PLAYBACK, ops: &snd_cmipci_playback_spdif_ops);
1890	snd_pcm_set_ops(pcm, direction: SNDRV_PCM_STREAM_CAPTURE, ops: &snd_cmipci_capture_spdif_ops);
1891
1892	pcm->private_data = cm;
1893	pcm->info_flags = 0;
1894	strscpy(pcm->name, "C-Media PCI IEC958");
1895	cm->pcm_spdif = pcm;
1896
1897	snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1898	data: &cm->pci->dev, size: 64*1024, max: 128*1024);
1899
1900	err = snd_pcm_add_chmap_ctls(pcm, stream: SNDRV_PCM_STREAM_PLAYBACK,
1901	chmap: snd_pcm_alt_chmaps, max_channels: cm->max_channels, private_value: 0,
1902	NULL);
1903	if (err < 0)
1904	return err;
1905
1906	return 0;
1907	}
1908
1909	/*
1910	* mixer interface:
1911	* - CM8338/8738 has a compatible mixer interface with SB16, but
1912	* lack of some elements like tone control, i/o gain and AGC.
1913	* - Access to native registers:
1914	* - A 3D switch
1915	* - Output mute switches
1916	*/
1917
1918	static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
1919	{
1920	outb(value: idx, port: s->iobase + CM_REG_SB16_ADDR);
1921	outb(value: data, port: s->iobase + CM_REG_SB16_DATA);
1922	}
1923
1924	static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
1925	{
1926	unsigned char v;
1927
1928	outb(value: idx, port: s->iobase + CM_REG_SB16_ADDR);
1929	v = inb(port: s->iobase + CM_REG_SB16_DATA);
1930	return v;
1931	}
1932
1933	/*
1934	* general mixer element
1935	*/
1936	struct cmipci_sb_reg {
1937	unsigned int left_reg, right_reg;
1938	unsigned int left_shift, right_shift;
1939	unsigned int mask;
1940	unsigned int invert: 1;
1941	unsigned int stereo: 1;
1942	};
1943
1944	#define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1945	((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1946
1947	#define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1948	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1949	.info = snd_cmipci_info_volume, \
1950	.get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1951	.private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1952	}
1953
1954	#define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1955	#define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1956	#define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1957	#define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1958
1959	static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
1960	{
1961	r->left_reg = val & 0xff;
1962	r->right_reg = (val >> 8) & 0xff;
1963	r->left_shift = (val >> 16) & 0x07;
1964	r->right_shift = (val >> 19) & 0x07;
1965	r->invert = (val >> 22) & 1;
1966	r->stereo = (val >> 23) & 1;
1967	r->mask = (val >> 24) & 0xff;
1968	}
1969
1970	static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
1971	struct snd_ctl_elem_info *uinfo)
1972	{
1973	struct cmipci_sb_reg reg;
1974
1975	cmipci_sb_reg_decode(r: &reg, val: kcontrol->private_value);
1976	uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
1977	uinfo->count = reg.stereo + 1;
1978	uinfo->value.integer.min = 0;
1979	uinfo->value.integer.max = reg.mask;
1980	return 0;
1981	}
1982
1983	static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
1984	struct snd_ctl_elem_value *ucontrol)
1985	{
1986	struct cmipci *cm = snd_kcontrol_chip(kcontrol);
1987	struct cmipci_sb_reg reg;
1988	int val;
1989
1990	cmipci_sb_reg_decode(r: &reg, val: kcontrol->private_value);
1991	guard(spinlock_irq)(l: &cm->reg_lock);
1992	val = (snd_cmipci_mixer_read(s: cm, idx: reg.left_reg) >> reg.left_shift) & reg.mask;
1993	if (reg.invert)
1994	val = reg.mask - val;
1995	ucontrol->value.integer.value[0] = val;
1996	if (reg.stereo) {
1997	val = (snd_cmipci_mixer_read(s: cm, idx: reg.right_reg) >> reg.right_shift) & reg.mask;
1998	if (reg.invert)
1999	val = reg.mask - val;
2000	ucontrol->value.integer.value[1] = val;
2001	}
2002	return 0;
2003	}
2004
2005	static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
2006	struct snd_ctl_elem_value *ucontrol)
2007	{
2008	struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2009	struct cmipci_sb_reg reg;
2010	int change;
2011	int left, right, oleft, oright;
2012
2013	cmipci_sb_reg_decode(r: &reg, val: kcontrol->private_value);
2014	left = ucontrol->value.integer.value[0] & reg.mask;
2015	if (reg.invert)
2016	left = reg.mask - left;
2017	left <<= reg.left_shift;
2018	if (reg.stereo) {
2019	right = ucontrol->value.integer.value[1] & reg.mask;
2020	if (reg.invert)
2021	right = reg.mask - right;
2022	right <<= reg.right_shift;
2023	} else
2024	right = 0;
2025	guard(spinlock_irq)(l: &cm->reg_lock);
2026	oleft = snd_cmipci_mixer_read(s: cm, idx: reg.left_reg);
2027	left |= oleft & ~(reg.mask << reg.left_shift);
2028	change = left != oleft;
2029	if (reg.stereo) {
2030	if (reg.left_reg != reg.right_reg) {
2031	snd_cmipci_mixer_write(s: cm, idx: reg.left_reg, data: left);
2032	oright = snd_cmipci_mixer_read(s: cm, idx: reg.right_reg);
2033	} else
2034	oright = left;
2035	right |= oright & ~(reg.mask << reg.right_shift);
2036	change |= right != oright;
2037	snd_cmipci_mixer_write(s: cm, idx: reg.right_reg, data: right);
2038	} else
2039	snd_cmipci_mixer_write(s: cm, idx: reg.left_reg, data: left);
2040	return change;
2041	}
2042
2043	/*
2044	* input route (left,right) -> (left,right)
2045	*/
2046	#define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
2047	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2048	.info = snd_cmipci_info_input_sw, \
2049	.get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
2050	.private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
2051	}
2052
2053	static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
2054	struct snd_ctl_elem_info *uinfo)
2055	{
2056	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
2057	uinfo->count = 4;
2058	uinfo->value.integer.min = 0;
2059	uinfo->value.integer.max = 1;
2060	return 0;
2061	}
2062
2063	static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
2064	struct snd_ctl_elem_value *ucontrol)
2065	{
2066	struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2067	struct cmipci_sb_reg reg;
2068	int val1, val2;
2069
2070	cmipci_sb_reg_decode(r: &reg, val: kcontrol->private_value);
2071	guard(spinlock_irq)(l: &cm->reg_lock);
2072	val1 = snd_cmipci_mixer_read(s: cm, idx: reg.left_reg);
2073	val2 = snd_cmipci_mixer_read(s: cm, idx: reg.right_reg);
2074	ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
2075	ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
2076	ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
2077	ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
2078	return 0;
2079	}
2080
2081	static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
2082	struct snd_ctl_elem_value *ucontrol)
2083	{
2084	struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2085	struct cmipci_sb_reg reg;
2086	int change;
2087	int val1, val2, oval1, oval2;
2088
2089	cmipci_sb_reg_decode(r: &reg, val: kcontrol->private_value);
2090	guard(spinlock_irq)(l: &cm->reg_lock);
2091	oval1 = snd_cmipci_mixer_read(s: cm, idx: reg.left_reg);
2092	oval2 = snd_cmipci_mixer_read(s: cm, idx: reg.right_reg);
2093	val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2094	val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
2095	val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
2096	val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
2097	val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
2098	val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
2099	change = val1 != oval1 || val2 != oval2;
2100	snd_cmipci_mixer_write(s: cm, idx: reg.left_reg, data: val1);
2101	snd_cmipci_mixer_write(s: cm, idx: reg.right_reg, data: val2);
2102	return change;
2103	}
2104
2105	/*
2106	* native mixer switches/volumes
2107	*/
2108
2109	#define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
2110	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2111	.info = snd_cmipci_info_native_mixer, \
2112	.get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2113	.private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
2114	}
2115
2116	#define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
2117	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2118	.info = snd_cmipci_info_native_mixer, \
2119	.get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2120	.private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
2121	}
2122
2123	#define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
2124	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2125	.info = snd_cmipci_info_native_mixer, \
2126	.get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2127	.private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
2128	}
2129
2130	#define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
2131	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2132	.info = snd_cmipci_info_native_mixer, \
2133	.get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
2134	.private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
2135	}
2136
2137	static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
2138	struct snd_ctl_elem_info *uinfo)
2139	{
2140	struct cmipci_sb_reg reg;
2141
2142	cmipci_sb_reg_decode(r: &reg, val: kcontrol->private_value);
2143	uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2144	uinfo->count = reg.stereo + 1;
2145	uinfo->value.integer.min = 0;
2146	uinfo->value.integer.max = reg.mask;
2147	return 0;
2148
2149	}
2150
2151	static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
2152	struct snd_ctl_elem_value *ucontrol)
2153	{
2154	struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2155	struct cmipci_sb_reg reg;
2156	unsigned char oreg, val;
2157
2158	cmipci_sb_reg_decode(r: &reg, val: kcontrol->private_value);
2159	guard(spinlock_irq)(l: &cm->reg_lock);
2160	oreg = inb(port: cm->iobase + reg.left_reg);
2161	val = (oreg >> reg.left_shift) & reg.mask;
2162	if (reg.invert)
2163	val = reg.mask - val;
2164	ucontrol->value.integer.value[0] = val;
2165	if (reg.stereo) {
2166	val = (oreg >> reg.right_shift) & reg.mask;
2167	if (reg.invert)
2168	val = reg.mask - val;
2169	ucontrol->value.integer.value[1] = val;
2170	}
2171	return 0;
2172	}
2173
2174	static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
2175	struct snd_ctl_elem_value *ucontrol)
2176	{
2177	struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2178	struct cmipci_sb_reg reg;
2179	unsigned char oreg, nreg, val;
2180
2181	cmipci_sb_reg_decode(r: &reg, val: kcontrol->private_value);
2182	guard(spinlock_irq)(l: &cm->reg_lock);
2183	oreg = inb(port: cm->iobase + reg.left_reg);
2184	val = ucontrol->value.integer.value[0] & reg.mask;
2185	if (reg.invert)
2186	val = reg.mask - val;
2187	nreg = oreg & ~(reg.mask << reg.left_shift);
2188	nreg |= (val << reg.left_shift);
2189	if (reg.stereo) {
2190	val = ucontrol->value.integer.value[1] & reg.mask;
2191	if (reg.invert)
2192	val = reg.mask - val;
2193	nreg &= ~(reg.mask << reg.right_shift);
2194	nreg |= (val << reg.right_shift);
2195	}
2196	outb(value: nreg, port: cm->iobase + reg.left_reg);
2197	return (nreg != oreg);
2198	}
2199
2200	/*
2201	* special case - check mixer sensitivity
2202	*/
2203	static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2204	struct snd_ctl_elem_value *ucontrol)
2205	{
2206	//struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2207	return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
2208	}
2209
2210	static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
2211	struct snd_ctl_elem_value *ucontrol)
2212	{
2213	struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2214	if (cm->mixer_insensitive) {
2215	/* ignored */
2216	return 0;
2217	}
2218	return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
2219	}
2220
2221
2222	static const struct snd_kcontrol_new snd_cmipci_mixers[] = {
2223	CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
2224	CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
2225	CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
2226	//CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2227	{ /* switch with sensitivity */
2228	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2229	.name = "PCM Playback Switch",
2230	.info = snd_cmipci_info_native_mixer,
2231	.get = snd_cmipci_get_native_mixer_sensitive,
2232	.put = snd_cmipci_put_native_mixer_sensitive,
2233	.private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
2234	},
2235	CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
2236	CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
2237	CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
2238	CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2239	CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
2240	CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2241	CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2242	CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
2243	CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2244	CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2245	CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
2246	CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2247	CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
2248	CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
2249	CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
2250	CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
2251	CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
2252	CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
2253	CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
2254	CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
2255	CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
2256	CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
2257	CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
2258	};
2259
2260	/*
2261	* other switches
2262	*/
2263
2264	struct cmipci_switch_args {
2265	int reg; /* register index */
2266	unsigned int mask; /* mask bits */
2267	unsigned int mask_on; /* mask bits to turn on */
2268	unsigned int is_byte: 1; /* byte access? */
2269	unsigned int ac3_sensitive: 1; /* access forbidden during
2270	* non-audio operation?
2271	*/
2272	};
2273
2274	#define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
2275
2276	static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2277	struct snd_ctl_elem_value *ucontrol,
2278	struct cmipci_switch_args *args)
2279	{
2280	unsigned int val;
2281	struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2282
2283	guard(spinlock_irq)(l: &cm->reg_lock);
2284	if (args->ac3_sensitive && cm->mixer_insensitive) {
2285	ucontrol->value.integer.value[0] = 0;
2286	return 0;
2287	}
2288	if (args->is_byte)
2289	val = inb(port: cm->iobase + args->reg);
2290	else
2291	val = snd_cmipci_read(cm, cmd: args->reg);
2292	ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
2293	return 0;
2294	}
2295
2296	static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
2297	struct snd_ctl_elem_value *ucontrol)
2298	{
2299	struct cmipci_switch_args *args;
2300	args = (struct cmipci_switch_args *)kcontrol->private_value;
2301	if (snd_BUG_ON(!args))
2302	return -EINVAL;
2303	return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
2304	}
2305
2306	static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2307	struct snd_ctl_elem_value *ucontrol,
2308	struct cmipci_switch_args *args)
2309	{
2310	unsigned int val;
2311	int change;
2312	struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2313
2314	guard(spinlock_irq)(l: &cm->reg_lock);
2315	if (args->ac3_sensitive && cm->mixer_insensitive) {
2316	/* ignored */
2317	return 0;
2318	}
2319	if (args->is_byte)
2320	val = inb(port: cm->iobase + args->reg);
2321	else
2322	val = snd_cmipci_read(cm, cmd: args->reg);
2323	change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
2324	args->mask_on : (args->mask & ~args->mask_on));
2325	if (change) {
2326	val &= ~args->mask;
2327	if (ucontrol->value.integer.value[0])
2328	val |= args->mask_on;
2329	else
2330	val |= (args->mask & ~args->mask_on);
2331	if (args->is_byte)
2332	outb(value: (unsigned char)val, port: cm->iobase + args->reg);
2333	else
2334	snd_cmipci_write(cm, cmd: args->reg, data: val);
2335	}
2336	return change;
2337	}
2338
2339	static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
2340	struct snd_ctl_elem_value *ucontrol)
2341	{
2342	struct cmipci_switch_args *args;
2343	args = (struct cmipci_switch_args *)kcontrol->private_value;
2344	if (snd_BUG_ON(!args))
2345	return -EINVAL;
2346	return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
2347	}
2348
2349	#define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2350	static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
2351	.reg = xreg, \
2352	.mask = xmask, \
2353	.mask_on = xmask_on, \
2354	.is_byte = xis_byte, \
2355	.ac3_sensitive = xac3, \
2356	}
2357
2358	#define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2359	DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2360
2361	#if 0 /* these will be controlled in pcm device */
2362	DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2363	DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2364	#endif
2365	DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
2366	DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
2367	DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
2368	DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2369	DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
2370	DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
2371	DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
2372	DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
2373	// DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2374	DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2375	DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
2376	/* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2377	DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
2378	DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
2379	#if CM_CH_PLAY == 1
2380	DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
2381	#else
2382	DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
2383	#endif
2384	DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
2385	// DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
2386	// DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
2387	// DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2388	DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
2389
2390	#define DEFINE_SWITCH(sname, stype, sarg) \
2391	{ .name = sname, \
2392	.iface = stype, \
2393	.info = snd_cmipci_uswitch_info, \
2394	.get = snd_cmipci_uswitch_get, \
2395	.put = snd_cmipci_uswitch_put, \
2396	.private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2397	}
2398
2399	#define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2400	#define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2401
2402
2403	/*
2404	* callbacks for spdif output switch
2405	* needs toggle two registers..
2406	*/
2407	static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
2408	struct snd_ctl_elem_value *ucontrol)
2409	{
2410	int changed;
2411	changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, args: &cmipci_switch_arg_spdif_enable);
2412	changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, args: &cmipci_switch_arg_spdo2dac);
2413	return changed;
2414	}
2415
2416	static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
2417	struct snd_ctl_elem_value *ucontrol)
2418	{
2419	struct cmipci *chip = snd_kcontrol_chip(kcontrol);
2420	int changed;
2421	changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, args: &cmipci_switch_arg_spdif_enable);
2422	changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, args: &cmipci_switch_arg_spdo2dac);
2423	if (changed) {
2424	if (ucontrol->value.integer.value[0]) {
2425	if (chip->spdif_playback_avail)
2426	snd_cmipci_set_bit(cm: chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2427	} else {
2428	if (chip->spdif_playback_avail)
2429	snd_cmipci_clear_bit(cm: chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
2430	}
2431	}
2432	chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
2433	return changed;
2434	}
2435
2436
2437	static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
2438	struct snd_ctl_elem_info *uinfo)
2439	{
2440	struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2441	static const char *const texts[3] = {
2442	"Line-In", "Rear Output", "Bass Output"
2443	};
2444
2445	return snd_ctl_enum_info(info: uinfo, channels: 1,
2446	items: cm->chip_version >= 39 ? 3 : 2, names: texts);
2447	}
2448
2449	static inline unsigned int get_line_in_mode(struct cmipci *cm)
2450	{
2451	unsigned int val;
2452	if (cm->chip_version >= 39) {
2453	val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
2454	if (val & (CM_CENTR2LIN | CM_BASE2LIN))
2455	return 2;
2456	}
2457	val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
2458	if (val & CM_REAR2LIN)
2459	return 1;
2460	return 0;
2461	}
2462
2463	static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
2464	struct snd_ctl_elem_value *ucontrol)
2465	{
2466	struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2467
2468	guard(spinlock_irq)(l: &cm->reg_lock);
2469	ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
2470	return 0;
2471	}
2472
2473	static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
2474	struct snd_ctl_elem_value *ucontrol)
2475	{
2476	struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2477	int change;
2478
2479	guard(spinlock_irq)(l: &cm->reg_lock);
2480	if (ucontrol->value.enumerated.item[0] == 2)
2481	change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2482	else
2483	change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
2484	if (ucontrol->value.enumerated.item[0] == 1)
2485	change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2486	else
2487	change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
2488	return change;
2489	}
2490
2491	static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
2492	struct snd_ctl_elem_info *uinfo)
2493	{
2494	static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
2495
2496	return snd_ctl_enum_info(info: uinfo, channels: 1, items: 2, names: texts);
2497	}
2498
2499	static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
2500	struct snd_ctl_elem_value *ucontrol)
2501	{
2502	struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2503
2504	/* same bit as spdi_phase */
2505	guard(spinlock_irq)(l: &cm->reg_lock);
2506	ucontrol->value.enumerated.item[0] =
2507	(snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
2508	return 0;
2509	}
2510
2511	static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
2512	struct snd_ctl_elem_value *ucontrol)
2513	{
2514	struct cmipci *cm = snd_kcontrol_chip(kcontrol);
2515	int change;
2516
2517	guard(spinlock_irq)(l: &cm->reg_lock);
2518	if (ucontrol->value.enumerated.item[0])
2519	change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2520	else
2521	change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
2522	return change;
2523	}
2524
2525	/* both for CM8338/8738 */
2526	static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
2527	DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
2528	{
2529	.name = "Line-In Mode",
2530	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2531	.info = snd_cmipci_line_in_mode_info,
2532	.get = snd_cmipci_line_in_mode_get,
2533	.put = snd_cmipci_line_in_mode_put,
2534	},
2535	};
2536
2537	/* for non-multichannel chips */
2538	static const struct snd_kcontrol_new snd_cmipci_nomulti_switch =
2539	DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
2540
2541	/* only for CM8738 */
2542	static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
2543	#if 0 /* controlled in pcm device */
2544	DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
2545	DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
2546	DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
2547	#endif
2548	// DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2549	{ .name = "IEC958 Output Switch",
2550	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2551	.info = snd_cmipci_uswitch_info,
2552	.get = snd_cmipci_spdout_enable_get,
2553	.put = snd_cmipci_spdout_enable_put,
2554	},
2555	DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
2556	DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
2557	DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
2558	// DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2559	DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
2560	DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
2561	};
2562
2563	/* only for model 033/037 */
2564	static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
2565	DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
2566	DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
2567	DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
2568	};
2569
2570	/* only for model 039 or later */
2571	static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
2572	DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
2573	DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
2574	{
2575	.name = "Mic-In Mode",
2576	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2577	.info = snd_cmipci_mic_in_mode_info,
2578	.get = snd_cmipci_mic_in_mode_get,
2579	.put = snd_cmipci_mic_in_mode_put,
2580	}
2581	};
2582
2583	/* card control switches */
2584	static const struct snd_kcontrol_new snd_cmipci_modem_switch =
2585	DEFINE_CARD_SWITCH("Modem", modem);
2586
2587
2588	static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
2589	{
2590	struct snd_card *card;
2591	const struct snd_kcontrol_new *sw;
2592	struct snd_kcontrol *kctl;
2593	unsigned int idx;
2594	int err;
2595
2596	if (snd_BUG_ON(!cm || !cm->card))
2597	return -EINVAL;
2598
2599	card = cm->card;
2600
2601	strscpy(card->mixername, "CMedia PCI");
2602
2603	scoped_guard(spinlock_irq, &cm->reg_lock) {
2604	snd_cmipci_mixer_write(s: cm, idx: 0x00, data: 0x00); /* mixer reset */
2605	}
2606
2607	for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
2608	if (cm->chip_version == 68) { // 8768 has no PCM volume
2609	if (!strcmp(snd_cmipci_mixers[idx].name,
2610	"PCM Playback Volume"))
2611	continue;
2612	}
2613	err = snd_ctl_add(card, kcontrol: snd_ctl_new1(kcontrolnew: &snd_cmipci_mixers[idx], private_data: cm));
2614	if (err < 0)
2615	return err;
2616	}
2617
2618	/* mixer switches */
2619	sw = snd_cmipci_mixer_switches;
2620	for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
2621	err = snd_ctl_add(card: cm->card, kcontrol: snd_ctl_new1(kcontrolnew: sw, private_data: cm));
2622	if (err < 0)
2623	return err;
2624	}
2625	if (! cm->can_multi_ch) {
2626	err = snd_ctl_add(card: cm->card, kcontrol: snd_ctl_new1(kcontrolnew: &snd_cmipci_nomulti_switch, private_data: cm));
2627	if (err < 0)
2628	return err;
2629	}
2630	if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
2631	cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
2632	sw = snd_cmipci_8738_mixer_switches;
2633	for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
2634	err = snd_ctl_add(card: cm->card, kcontrol: snd_ctl_new1(kcontrolnew: sw, private_data: cm));
2635	if (err < 0)
2636	return err;
2637	}
2638	if (cm->can_ac3_hw) {
2639	kctl = snd_ctl_new1(kcontrolnew: &snd_cmipci_spdif_default, private_data: cm);
2640	kctl->id.device = pcm_spdif_device;
2641	err = snd_ctl_add(card, kcontrol: kctl);
2642	if (err < 0)
2643	return err;
2644	kctl = snd_ctl_new1(kcontrolnew: &snd_cmipci_spdif_mask, private_data: cm);
2645	kctl->id.device = pcm_spdif_device;
2646	err = snd_ctl_add(card, kcontrol: kctl);
2647	if (err < 0)
2648	return err;
2649	kctl = snd_ctl_new1(kcontrolnew: &snd_cmipci_spdif_stream, private_data: cm);
2650	kctl->id.device = pcm_spdif_device;
2651	err = snd_ctl_add(card, kcontrol: kctl);
2652	if (err < 0)
2653	return err;
2654	}
2655	if (cm->chip_version <= 37) {
2656	sw = snd_cmipci_old_mixer_switches;
2657	for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
2658	err = snd_ctl_add(card: cm->card, kcontrol: snd_ctl_new1(kcontrolnew: sw, private_data: cm));
2659	if (err < 0)
2660	return err;
2661	}
2662	}
2663	}
2664	if (cm->chip_version >= 39) {
2665	sw = snd_cmipci_extra_mixer_switches;
2666	for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
2667	err = snd_ctl_add(card: cm->card, kcontrol: snd_ctl_new1(kcontrolnew: sw, private_data: cm));
2668	if (err < 0)
2669	return err;
2670	}
2671	}
2672
2673	/* card switches */
2674	/*
2675	* newer chips don't have the register bits to force modem link
2676	* detection; the bit that was FLINKON now mutes CH1
2677	*/
2678	if (cm->chip_version < 39) {
2679	err = snd_ctl_add(card: cm->card,
2680	kcontrol: snd_ctl_new1(kcontrolnew: &snd_cmipci_modem_switch, private_data: cm));
2681	if (err < 0)
2682	return err;
2683	}
2684
2685	for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
2686	struct snd_kcontrol *ctl;
2687	ctl = snd_ctl_find_id_mixer(card: cm->card, name: cm_saved_mixer[idx].name);
2688	if (ctl)
2689	cm->mixer_res_ctl[idx] = ctl;
2690	}
2691
2692	return 0;
2693	}
2694
2695
2696	/*
2697	* proc interface
2698	*/
2699
2700	static void snd_cmipci_proc_read(struct snd_info_entry *entry,
2701	struct snd_info_buffer *buffer)
2702	{
2703	struct cmipci *cm = entry->private_data;
2704	int i, v;
2705
2706	snd_iprintf(buffer, "%s\n", cm->card->longname);
2707	for (i = 0; i < 0x94; i++) {
2708	if (i == 0x28)
2709	i = 0x90;
2710	v = inb(port: cm->iobase + i);
2711	if (i % 4 == 0)
2712	snd_iprintf(buffer, "\n%02x:", i);
2713	snd_iprintf(buffer, " %02x", v);
2714	}
2715	snd_iprintf(buffer, "\n");
2716	}
2717
2718	static void snd_cmipci_proc_init(struct cmipci *cm)
2719	{
2720	snd_card_ro_proc_new(card: cm->card, name: "cmipci", private_data: cm, read: snd_cmipci_proc_read);
2721	}
2722
2723	static const struct pci_device_id snd_cmipci_ids[] = {
2724	{PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
2725	{PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
2726	{PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2727	{PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
2728	{PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
2729	{0,},
2730	};
2731
2732
2733	/*
2734	* check chip version and capabilities
2735	* driver name is modified according to the chip model
2736	*/
2737	static void query_chip(struct cmipci *cm)
2738	{
2739	unsigned int detect;
2740
2741	/* check reg 0Ch, bit 24-31 */
2742	detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
2743	if (! detect) {
2744	/* check reg 08h, bit 24-28 */
2745	detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
2746	switch (detect) {
2747	case 0:
2748	cm->chip_version = 33;
2749	if (cm->do_soft_ac3)
2750	cm->can_ac3_sw = 1;
2751	else
2752	cm->can_ac3_hw = 1;
2753	break;
2754	case CM_CHIP_037:
2755	cm->chip_version = 37;
2756	cm->can_ac3_hw = 1;
2757	break;
2758	default:
2759	cm->chip_version = 39;
2760	cm->can_ac3_hw = 1;
2761	break;
2762	}
2763	cm->max_channels = 2;
2764	} else {
2765	if (detect & CM_CHIP_039) {
2766	cm->chip_version = 39;
2767	if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
2768	cm->max_channels = 6;
2769	else
2770	cm->max_channels = 4;
2771	} else if (detect & CM_CHIP_8768) {
2772	cm->chip_version = 68;
2773	cm->max_channels = 8;
2774	cm->can_96k = 1;
2775	} else {
2776	cm->chip_version = 55;
2777	cm->max_channels = 6;
2778	cm->can_96k = 1;
2779	}
2780	cm->can_ac3_hw = 1;
2781	cm->can_multi_ch = 1;
2782	}
2783	}
2784
2785	#ifdef SUPPORT_JOYSTICK
2786	static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
2787	{
2788	static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2789	struct gameport *gp;
2790	struct resource *r = NULL;
2791	int i, io_port = 0;
2792
2793	if (joystick_port[dev] == 0)
2794	return -ENODEV;
2795
2796	if (joystick_port[dev] == 1) { /* auto-detect */
2797	for (i = 0; ports[i]; i++) {
2798	io_port = ports[i];
2799	r = devm_request_region(&cm->pci->dev, io_port, 1,
2800	"CMIPCI gameport");
2801	if (r)
2802	break;
2803	}
2804	} else {
2805	io_port = joystick_port[dev];
2806	r = devm_request_region(&cm->pci->dev, io_port, 1,
2807	"CMIPCI gameport");
2808	}
2809
2810	if (!r) {
2811	dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
2812	return -EBUSY;
2813	}
2814
2815	cm->gameport = gp = gameport_allocate_port();
2816	if (!gp) {
2817	dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
2818	return -ENOMEM;
2819	}
2820	gameport_set_name(gameport: gp, name: "C-Media Gameport");
2821	gameport_set_phys(gameport: gp, fmt: "pci%s/gameport0", pci_name(pdev: cm->pci));
2822	gameport_set_dev_parent(gp, &cm->pci->dev);
2823	gp->io = io_port;
2824
2825	snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2826
2827	gameport_register_port(cm->gameport);
2828
2829	return 0;
2830	}
2831
2832	static void snd_cmipci_free_gameport(struct cmipci *cm)
2833	{
2834	if (cm->gameport) {
2835	gameport_unregister_port(gameport: cm->gameport);
2836	cm->gameport = NULL;
2837
2838	snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
2839	}
2840	}
2841	#else
2842	static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
2843	static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
2844	#endif
2845
2846	static void snd_cmipci_free(struct snd_card *card)
2847	{
2848	struct cmipci *cm = card->private_data;
2849
2850	snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2851	snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
2852	snd_cmipci_write(cm, CM_REG_INT_HLDCLR, data: 0); /* disable ints */
2853	snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2854	snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2855	snd_cmipci_write(cm, CM_REG_FUNCTRL0, data: 0); /* disable channels */
2856	snd_cmipci_write(cm, CM_REG_FUNCTRL1, data: 0);
2857
2858	/* reset mixer */
2859	snd_cmipci_mixer_write(s: cm, idx: 0, data: 0);
2860
2861	snd_cmipci_free_gameport(cm);
2862	}
2863
2864	static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
2865	{
2866	long iosynth;
2867	unsigned int val;
2868	struct snd_opl3 *opl3;
2869	int err;
2870
2871	if (!fm_port)
2872	goto disable_fm;
2873
2874	if (cm->chip_version >= 39) {
2875	/* first try FM regs in PCI port range */
2876	iosynth = cm->iobase + CM_REG_FM_PCI;
2877	err = snd_opl3_create(card: cm->card, l_port: iosynth, r_port: iosynth + 2,
2878	OPL3_HW_OPL3, integrated: 1, opl3: &opl3);
2879	} else {
2880	err = -EIO;
2881	}
2882	if (err < 0) {
2883	/* then try legacy ports */
2884	val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
2885	iosynth = fm_port;
2886	switch (iosynth) {
2887	case 0x3E8: val |= CM_FMSEL_3E8; break;
2888	case 0x3E0: val |= CM_FMSEL_3E0; break;
2889	case 0x3C8: val |= CM_FMSEL_3C8; break;
2890	case 0x388: val |= CM_FMSEL_388; break;
2891	default:
2892	goto disable_fm;
2893	}
2894	snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, data: val);
2895	/* enable FM */
2896	snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2897
2898	if (snd_opl3_create(card: cm->card, l_port: iosynth, r_port: iosynth + 2,
2899	OPL3_HW_OPL3, integrated: 0, opl3: &opl3) < 0) {
2900	dev_err(cm->card->dev,
2901	"no OPL device at %#lx, skipping...\n",
2902	iosynth);
2903	goto disable_fm;
2904	}
2905	}
2906	err = snd_opl3_hwdep_new(opl3, device: 0, seq_device: 1, NULL);
2907	if (err < 0) {
2908	dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
2909	return err;
2910	}
2911	return 0;
2912
2913	disable_fm:
2914	snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
2915	snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
2916	return 0;
2917	}
2918
2919	static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
2920	int dev)
2921	{
2922	struct cmipci *cm = card->private_data;
2923	int err;
2924	unsigned int val;
2925	long iomidi = 0;
2926	int integrated_midi = 0;
2927	char modelstr[16];
2928	int pcm_index, pcm_spdif_index;
2929	static const struct pci_device_id intel_82437vx[] = {
2930	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
2931	{ },
2932	};
2933
2934	err = pcim_enable_device(pdev: pci);
2935	if (err < 0)
2936	return err;
2937
2938	spin_lock_init(&cm->reg_lock);
2939	mutex_init(&cm->open_mutex);
2940	cm->device = pci->device;
2941	cm->card = card;
2942	cm->pci = pci;
2943	cm->irq = -1;
2944	cm->channel[0].ch = 0;
2945	cm->channel[1].ch = 1;
2946	cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
2947
2948	err = pcim_request_all_regions(pdev: pci, name: card->driver);
2949	if (err < 0)
2950	return err;
2951	cm->iobase = pci_resource_start(pci, 0);
2952
2953	if (devm_request_irq(dev: &pci->dev, irq: pci->irq, handler: snd_cmipci_interrupt,
2954	IRQF_SHARED, KBUILD_MODNAME, dev_id: cm)) {
2955	dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2956	return -EBUSY;
2957	}
2958	cm->irq = pci->irq;
2959	card->sync_irq = cm->irq;
2960	card->private_free = snd_cmipci_free;
2961
2962	pci_set_master(dev: cm->pci);
2963
2964	/*
2965	* check chip version, max channels and capabilities
2966	*/
2967
2968	cm->chip_version = 0;
2969	cm->max_channels = 2;
2970	cm->do_soft_ac3 = soft_ac3[dev];
2971
2972	if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
2973	pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
2974	query_chip(cm);
2975	/* added -MCx suffix for chip supporting multi-channels */
2976	if (cm->can_multi_ch) {
2977	int l = strlen(cm->card->driver);
2978	scnprintf(buf: cm->card->driver + l, size: sizeof(cm->card->driver) - l,
2979	fmt: "-MC%d", cm->max_channels);
2980	} else if (cm->can_ac3_sw)
2981	strlcat(p: cm->card->driver, q: "-SWIEC", avail: sizeof(cm->card->driver));
2982
2983	cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2984	cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
2985
2986	#if CM_CH_PLAY == 1
2987	cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
2988	#else
2989	cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
2990	#endif
2991
2992	/* initialize codec registers */
2993	snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
2994	snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
2995	snd_cmipci_write(cm, CM_REG_INT_HLDCLR, data: 0); /* disable ints */
2996	snd_cmipci_ch_reset(cm, CM_CH_PLAY);
2997	snd_cmipci_ch_reset(cm, CM_CH_CAPT);
2998	snd_cmipci_write(cm, CM_REG_FUNCTRL0, data: 0); /* disable channels */
2999	snd_cmipci_write(cm, CM_REG_FUNCTRL1, data: 0);
3000
3001	snd_cmipci_write(cm, CM_REG_CHFORMAT, data: 0);
3002	snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
3003	#if CM_CH_PLAY == 1
3004	snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3005	#else
3006	snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
3007	#endif
3008	if (cm->chip_version) {
3009	snd_cmipci_write_b(cm, CM_REG_EXT_MISC, data: 0x20); /* magic */
3010	snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, data: 0x09); /* more magic */
3011	}
3012	/* Set Bus Master Request */
3013	snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
3014
3015	/* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
3016	switch (pci->device) {
3017	case PCI_DEVICE_ID_CMEDIA_CM8738:
3018	case PCI_DEVICE_ID_CMEDIA_CM8738B:
3019	if (!pci_dev_present(ids: intel_82437vx))
3020	snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
3021	break;
3022	default:
3023	break;
3024	}
3025
3026	if (cm->chip_version < 68) {
3027	val = pci->device < 0x110 ? 8338 : 8738;
3028	} else {
3029	switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
3030	case 0:
3031	val = 8769;
3032	break;
3033	case 2:
3034	val = 8762;
3035	break;
3036	default:
3037	switch ((pci->subsystem_vendor << 16) |
3038	pci->subsystem_device) {
3039	case 0x13f69761:
3040	case 0x584d3741:
3041	case 0x584d3751:
3042	case 0x584d3761:
3043	case 0x584d3771:
3044	case 0x72848384:
3045	val = 8770;
3046	break;
3047	default:
3048	val = 8768;
3049	break;
3050	}
3051	}
3052	}
3053	sprintf(buf: card->shortname, fmt: "C-Media CMI%u", val);
3054	if (cm->chip_version < 68)
3055	scnprintf(buf: modelstr, size: sizeof(modelstr),
3056	fmt: " (model %d)", cm->chip_version);
3057	else
3058	modelstr[0] = '\0';
3059	scnprintf(buf: card->longname, size: sizeof(card->longname),
3060	fmt: "%s%s at %#lx, irq %i",
3061	card->shortname, modelstr, cm->iobase, cm->irq);
3062
3063	if (cm->chip_version >= 39) {
3064	val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
3065	if (val != 0x00 && val != 0xff) {
3066	if (mpu_port[dev])
3067	iomidi = cm->iobase + CM_REG_MPU_PCI;
3068	integrated_midi = 1;
3069	}
3070	}
3071	if (!integrated_midi) {
3072	val = 0;
3073	iomidi = mpu_port[dev];
3074	switch (iomidi) {
3075	case 0x320: val = CM_VMPU_320; break;
3076	case 0x310: val = CM_VMPU_310; break;
3077	case 0x300: val = CM_VMPU_300; break;
3078	case 0x330: val = CM_VMPU_330; break;
3079	default:
3080	iomidi = 0; break;
3081	}
3082	if (iomidi > 0) {
3083	snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, data: val);
3084	/* enable UART */
3085	snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
3086	if (inb(port: iomidi + 1) == 0xff) {
3087	dev_err(cm->card->dev,
3088	"cannot enable MPU-401 port at %#lx\n",
3089	iomidi);
3090	snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
3091	CM_UART_EN);
3092	iomidi = 0;
3093	}
3094	}
3095	}
3096
3097	if (cm->chip_version < 68) {
3098	err = snd_cmipci_create_fm(cm, fm_port: fm_port[dev]);
3099	if (err < 0)
3100	return err;
3101	}
3102
3103	/* reset mixer */
3104	snd_cmipci_mixer_write(s: cm, idx: 0, data: 0);
3105
3106	snd_cmipci_proc_init(cm);
3107
3108	/* create pcm devices */
3109	pcm_index = pcm_spdif_index = 0;
3110	err = snd_cmipci_pcm_new(cm, device: pcm_index);
3111	if (err < 0)
3112	return err;
3113	pcm_index++;
3114	err = snd_cmipci_pcm2_new(cm, device: pcm_index);
3115	if (err < 0)
3116	return err;
3117	pcm_index++;
3118	if (cm->can_ac3_hw || cm->can_ac3_sw) {
3119	pcm_spdif_index = pcm_index;
3120	err = snd_cmipci_pcm_spdif_new(cm, device: pcm_index);
3121	if (err < 0)
3122	return err;
3123	}
3124
3125	/* create mixer interface & switches */
3126	err = snd_cmipci_mixer_new(cm, pcm_spdif_device: pcm_spdif_index);
3127	if (err < 0)
3128	return err;
3129
3130	if (iomidi > 0) {
3131	err = snd_mpu401_uart_new(card, device: 0, MPU401_HW_CMIPCI,
3132	port: iomidi,
3133	info_flags: (integrated_midi ?
3134	MPU401_INFO_INTEGRATED : 0) |
3135	MPU401_INFO_IRQ_HOOK,
3136	irq: -1, rrawmidi: &cm->rmidi);
3137	if (err < 0)
3138	dev_err(cm->card->dev,
3139	"no UART401 device at 0x%lx\n", iomidi);
3140	}
3141
3142	#ifdef USE_VAR48KRATE
3143	for (val = 0; val < ARRAY_SIZE(rates); val++)
3144	snd_cmipci_set_pll(cm, rates[val], val);
3145
3146	/*
3147	* (Re-)Enable external switch spdo_48k
3148	*/
3149	snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
3150	#endif /* USE_VAR48KRATE */
3151
3152	if (snd_cmipci_create_gameport(cm, dev) < 0)
3153	snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
3154
3155	return 0;
3156	}
3157
3158	/*
3159	*/
3160
3161	MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
3162
3163	static int snd_cmipci_probe(struct pci_dev *pci,
3164	const struct pci_device_id *pci_id)
3165	{
3166	static int dev;
3167	struct snd_card *card;
3168	int err;
3169
3170	if (dev >= SNDRV_CARDS)
3171	return -ENODEV;
3172	if (! enable[dev]) {
3173	dev++;
3174	return -ENOENT;
3175	}
3176
3177	err = snd_devm_card_new(parent: &pci->dev, idx: index[dev], xid: id[dev], THIS_MODULE,
3178	extra_size: sizeof(struct cmipci), card_ret: &card);
3179	if (err < 0)
3180	return err;
3181
3182	switch (pci->device) {
3183	case PCI_DEVICE_ID_CMEDIA_CM8738:
3184	case PCI_DEVICE_ID_CMEDIA_CM8738B:
3185	strscpy(card->driver, "CMI8738");
3186	break;
3187	case PCI_DEVICE_ID_CMEDIA_CM8338A:
3188	case PCI_DEVICE_ID_CMEDIA_CM8338B:
3189	strscpy(card->driver, "CMI8338");
3190	break;
3191	default:
3192	strscpy(card->driver, "CMIPCI");
3193	break;
3194	}
3195
3196	err = snd_cmipci_create(card, pci, dev);
3197	if (err < 0)
3198	goto error;
3199
3200	err = snd_card_register(card);
3201	if (err < 0)
3202	goto error;
3203
3204	pci_set_drvdata(pdev: pci, data: card);
3205	dev++;
3206	return 0;
3207
3208	error:
3209	snd_card_free(card);
3210	return err;
3211	}
3212
3213	/*
3214	* power management
3215	*/
3216	static const unsigned char saved_regs[] = {
3217	CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
3218	CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_AUX_VOL, CM_REG_PLL,
3219	CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
3220	CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
3221	CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
3222	};
3223
3224	static const unsigned char saved_mixers[] = {
3225	SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
3226	SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
3227	SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
3228	SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
3229	SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
3230	SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
3231	CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
3232	SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
3233	};
3234
3235	static int snd_cmipci_suspend(struct device *dev)
3236	{
3237	struct snd_card *card = dev_get_drvdata(dev);
3238	struct cmipci *cm = card->private_data;
3239	int i;
3240
3241	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3242
3243	/* save registers */
3244	for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3245	cm->saved_regs[i] = snd_cmipci_read(cm, cmd: saved_regs[i]);
3246	for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3247	cm->saved_mixers[i] = snd_cmipci_mixer_read(s: cm, idx: saved_mixers[i]);
3248
3249	/* disable ints */
3250	snd_cmipci_write(cm, CM_REG_INT_HLDCLR, data: 0);
3251	return 0;
3252	}
3253
3254	static int snd_cmipci_resume(struct device *dev)
3255	{
3256	struct snd_card *card = dev_get_drvdata(dev);
3257	struct cmipci *cm = card->private_data;
3258	int i;
3259
3260	/* reset / initialize to a sane state */
3261	snd_cmipci_write(cm, CM_REG_INT_HLDCLR, data: 0);
3262	snd_cmipci_ch_reset(cm, CM_CH_PLAY);
3263	snd_cmipci_ch_reset(cm, CM_CH_CAPT);
3264	snd_cmipci_mixer_write(s: cm, idx: 0, data: 0);
3265
3266	/* restore registers */
3267	for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3268	snd_cmipci_write(cm, cmd: saved_regs[i], data: cm->saved_regs[i]);
3269	for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
3270	snd_cmipci_mixer_write(s: cm, idx: saved_mixers[i], data: cm->saved_mixers[i]);
3271
3272	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3273	return 0;
3274	}
3275
3276	static DEFINE_SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
3277
3278	static struct pci_driver cmipci_driver = {
3279	.name = KBUILD_MODNAME,
3280	.id_table = snd_cmipci_ids,
3281	.probe = snd_cmipci_probe,
3282	.driver = {
3283	.pm = &snd_cmipci_pm,
3284	},
3285	};
3286
3287	module_pci_driver(cmipci_driver);
3288