1/* SPDX-License-Identifier: MIT */
2/* Copyright © 2025 Intel Corporation */
3
4#ifndef __INTEL_DISPLAY_REGS_H__
5#define __INTEL_DISPLAY_REGS_H__
6
7#include "intel_display_reg_defs.h"
8
9#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
10#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
11#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
12
13#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
14#define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
15#define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
16#define DPIO_SFR_BYPASS (1 << 1)
17#define DPIO_CMNRST (1 << 0)
18
19#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
20#define MIPIO_RST_CTRL (1 << 2)
21
22#define _BXT_PHY_CTL_DDI_A 0x64C00
23#define _BXT_PHY_CTL_DDI_B 0x64C10
24#define _BXT_PHY_CTL_DDI_C 0x64C20
25#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
26#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
27#define BXT_PHY_LANE_ENABLED (1 << 8)
28#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
29 _BXT_PHY_CTL_DDI_B)
30
31#define _PHY_CTL_FAMILY_DDI 0x64C90
32#define _PHY_CTL_FAMILY_EDP 0x64C80
33#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
34#define COMMON_RESET_DIS (1 << 31)
35#define BXT_PHY_CTL_FAMILY(phy) \
36 _MMIO(_PICK_EVEN_2RANGES(phy, 1, \
37 _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \
38 _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C))
39
40/* UAIMI scratch pad register 1 */
41#define UAIMI_SPR1 _MMIO(0x4F074)
42/* SKL VccIO mask */
43#define SKL_VCCIO_MASK 0x1
44/* SKL balance leg register */
45#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
46/* I_boost values */
47#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
48#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
49/* Balance leg disable bits */
50#define BALANCE_LEG_DISABLE_SHIFT 23
51#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
52
53#define ILK_GTT_FAULT _MMIO(0x44040) /* ilk/snb */
54#define GTT_FAULT_INVALID_GTT_PTE (1 << 7)
55#define GTT_FAULT_INVALID_PTE_DATA (1 << 6)
56#define GTT_FAULT_CURSOR_B_FAULT (1 << 5)
57#define GTT_FAULT_CURSOR_A_FAULT (1 << 4)
58#define GTT_FAULT_SPRITE_B_FAULT (1 << 3)
59#define GTT_FAULT_SPRITE_A_FAULT (1 << 2)
60#define GTT_FAULT_PRIMARY_B_FAULT (1 << 1)
61#define GTT_FAULT_PRIMARY_A_FAULT (1 << 0)
62
63#define DERRMR _MMIO(0x44050)
64/* Note that HBLANK events are reserved on bdw+ */
65#define DERRMR_PIPEA_SCANLINE (1 << 0)
66#define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1)
67#define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
68#define DERRMR_PIPEA_VBLANK (1 << 3)
69#define DERRMR_PIPEA_HBLANK (1 << 5)
70#define DERRMR_PIPEB_SCANLINE (1 << 8)
71#define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
72#define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
73#define DERRMR_PIPEB_VBLANK (1 << 11)
74#define DERRMR_PIPEB_HBLANK (1 << 13)
75/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
76#define DERRMR_PIPEC_SCANLINE (1 << 14)
77#define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15)
78#define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20)
79#define DERRMR_PIPEC_VBLANK (1 << 21)
80#define DERRMR_PIPEC_HBLANK (1 << 22)
81
82#define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \
83 VLV_IER, \
84 VLV_IIR)
85
86#define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0)
87#define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4)
88#define VLV_ESR _MMIO(VLV_DISPLAY_BASE + 0x20b8)
89#define VLV_ERROR_GUNIT_TLB_DATA (1 << 6)
90#define VLV_ERROR_GUNIT_TLB_PTE (1 << 5)
91#define VLV_ERROR_PAGE_TABLE (1 << 4)
92#define VLV_ERROR_CLAIM (1 << 0)
93
94#define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR)
95
96#define _MBUS_ABOX0_CTL 0x45038
97#define _MBUS_ABOX1_CTL 0x45048
98#define _MBUS_ABOX2_CTL 0x4504C
99#define MBUS_ABOX_CTL(x) \
100 _MMIO(_PICK_EVEN_2RANGES(x, 2, \
101 _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \
102 _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL))
103
104#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
105#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
106#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
107#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
108#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
109#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
110#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
111#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
112
113#define IPS_CTL _MMIO(0x43408)
114#define IPS_ENABLE REG_BIT(31)
115#define IPS_FALSE_COLOR REG_BIT(4)
116
117/*
118 * Clock control & power management
119 */
120#define _DPLL_A 0x6014
121#define _DPLL_B 0x6018
122#define _CHV_DPLL_C 0x6030
123#define DPLL(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
124 (pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
125
126#define VGA0 _MMIO(0x6000)
127#define VGA1 _MMIO(0x6004)
128#define VGA_PD _MMIO(0x6010)
129#define VGA0_PD_P2_DIV_4 (1 << 7)
130#define VGA0_PD_P1_DIV_2 (1 << 5)
131#define VGA0_PD_P1_SHIFT 0
132#define VGA0_PD_P1_MASK (0x1f << 0)
133#define VGA1_PD_P2_DIV_4 (1 << 15)
134#define VGA1_PD_P1_DIV_2 (1 << 13)
135#define VGA1_PD_P1_SHIFT 8
136#define VGA1_PD_P1_MASK (0x1f << 8)
137#define DPLL_VCO_ENABLE (1 << 31)
138#define DPLL_SDVO_HIGH_SPEED (1 << 30)
139#define DPLL_DVO_2X_MODE (1 << 30)
140#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
141#define DPLL_SYNCLOCK_ENABLE (1 << 29)
142#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
143#define DPLL_VGA_MODE_DIS (1 << 28)
144#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
145#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
146#define DPLL_MODE_MASK (3 << 26)
147#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
148#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
149#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
150#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
151#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
152#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
153#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
154#define DPLL_LOCK_VLV (1 << 15)
155#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
156#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
157#define DPLL_SSC_REF_CLK_CHV (1 << 13)
158#define DPLL_PORTC_READY_MASK (0xf << 4)
159#define DPLL_PORTB_READY_MASK (0xf)
160
161#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
162
163/* Additional CHV pll/phy registers */
164#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
165#define DPLL_PORTD_READY_MASK (0xf)
166#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
167#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
168#define PHY_LDO_DELAY_0NS 0x0
169#define PHY_LDO_DELAY_200NS 0x1
170#define PHY_LDO_DELAY_600NS 0x2
171#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
172#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
173#define PHY_CH_SU_PSR 0x1
174#define PHY_CH_DEEP_PSR 0x7
175#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
176#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
177#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
178#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
179#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
180#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
181
182/*
183 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
184 * this field (only one bit may be set).
185 */
186#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
187#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
188#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
189/* i830, required in DVO non-gang */
190#define PLL_P2_DIVIDE_BY_4 (1 << 23)
191#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
192#define PLL_REF_INPUT_DREFCLK (0 << 13)
193#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
194#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
195#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
196#define PLL_REF_INPUT_MASK (3 << 13)
197#define PLL_LOAD_PULSE_PHASE_SHIFT 9
198/* Ironlake */
199# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
200# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
201# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
202# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
203# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
204
205/*
206 * Parallel to Serial Load Pulse phase selection.
207 * Selects the phase for the 10X DPLL clock for the PCIe
208 * digital display port. The range is 4 to 13; 10 or more
209 * is just a flip delay. The default is 6
210 */
211#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
212#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
213/*
214 * SDVO multiplier for 945G/GM. Not used on 965.
215 */
216#define SDVO_MULTIPLIER_MASK 0x000000ff
217#define SDVO_MULTIPLIER_SHIFT_HIRES 4
218#define SDVO_MULTIPLIER_SHIFT_VGA 0
219
220#define _DPLL_A_MD 0x601c
221#define _DPLL_B_MD 0x6020
222#define _CHV_DPLL_C_MD 0x603c
223#define DPLL_MD(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
224 (pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
225
226/*
227 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
228 *
229 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
230 */
231#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
232#define DPLL_MD_UDI_DIVIDER_SHIFT 24
233/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
234#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
235#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
236/*
237 * SDVO/UDI pixel multiplier.
238 *
239 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
240 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
241 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
242 * dummy bytes in the datastream at an increased clock rate, with both sides of
243 * the link knowing how many bytes are fill.
244 *
245 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
246 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
247 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
248 * through an SDVO command.
249 *
250 * This register field has values of multiplication factor minus 1, with
251 * a maximum multiplier of 5 for SDVO.
252 */
253#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
254#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
255/*
256 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
257 * This best be set to the default value (3) or the CRT won't work. No,
258 * I don't entirely understand what this does...
259 */
260#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
261#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
262
263#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
264
265#define _FPA0 0x6040
266#define _FPA1 0x6044
267#define _FPB0 0x6048
268#define _FPB1 0x604c
269#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
270#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
271#define FP_N_DIV_MASK 0x003f0000
272#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
273#define FP_N_DIV_SHIFT 16
274#define FP_M1_DIV_MASK 0x00003f00
275#define FP_M1_DIV_SHIFT 8
276#define FP_M2_DIV_MASK 0x0000003f
277#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
278#define FP_M2_DIV_SHIFT 0
279
280#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
281#define FW_CSPWRDWNEN (1 << 15)
282
283#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
284
285#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
286#define CDCLK_FREQ_SHIFT 4
287#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
288#define CZCLK_FREQ_MASK 0xf
289
290#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
291#define PFI_CREDIT_63 (9 << 28) /* chv only */
292#define PFI_CREDIT_31 (8 << 28) /* chv only */
293#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
294#define PFI_CREDIT_RESEND (1 << 27)
295#define VGA_FAST_MODE_DISABLE (1 << 14)
296
297#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
298
299#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
300
301/*
302 * Overlay regs
303 */
304#define OVADD _MMIO(0x30000)
305#define DOVSTA _MMIO(0x30008)
306#define OC_BUF (0x3 << 20)
307#define OGAMC5 _MMIO(0x30010)
308#define OGAMC4 _MMIO(0x30014)
309#define OGAMC3 _MMIO(0x30018)
310#define OGAMC2 _MMIO(0x3001c)
311#define OGAMC1 _MMIO(0x30020)
312#define OGAMC0 _MMIO(0x30024)
313
314#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
315#define BXT_GMBUS_GATING_DIS (1 << 14)
316#define DG2_DPFC_GATING_DIS REG_BIT(31)
317
318#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
319#define DPCE_GATING_DIS REG_BIT(17)
320
321#define _CLKGATE_DIS_PSL_A 0x46520
322#define _CLKGATE_DIS_PSL_B 0x46524
323#define _CLKGATE_DIS_PSL_C 0x46528
324#define DUPS1_GATING_DIS (1 << 15)
325#define DUPS2_GATING_DIS (1 << 19)
326#define DUPS3_GATING_DIS (1 << 23)
327#define CURSOR_GATING_DIS REG_BIT(28)
328#define DPF_GATING_DIS (1 << 10)
329#define DPF_RAM_GATING_DIS (1 << 9)
330#define DPFR_GATING_DIS (1 << 8)
331
332#define CLKGATE_DIS_PSL(pipe) \
333 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
334
335#define _CLKGATE_DIS_PSL_EXT_A 0x4654C
336#define _CLKGATE_DIS_PSL_EXT_B 0x46550
337#define PIPEDMC_GATING_DIS REG_BIT(12)
338
339#define CLKGATE_DIS_PSL_EXT(pipe) \
340 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)
341
342/*
343 * Display engine regs
344 */
345/* Pipe/transcoder A timing regs */
346#define _TRANS_HTOTAL_A 0x60000
347#define _TRANS_HTOTAL_B 0x61000
348#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
349#define HTOTAL_MASK REG_GENMASK(31, 16)
350#define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal))
351#define HACTIVE_MASK REG_GENMASK(15, 0)
352#define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay))
353
354#define _TRANS_HBLANK_A 0x60004
355#define _TRANS_HBLANK_B 0x61004
356#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
357#define HBLANK_END_MASK REG_GENMASK(31, 16)
358#define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end))
359#define HBLANK_START_MASK REG_GENMASK(15, 0)
360#define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start))
361
362#define _TRANS_HSYNC_A 0x60008
363#define _TRANS_HSYNC_B 0x61008
364#define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
365#define HSYNC_END_MASK REG_GENMASK(31, 16)
366#define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end))
367#define HSYNC_START_MASK REG_GENMASK(15, 0)
368#define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start))
369
370#define _TRANS_VTOTAL_A 0x6000c
371#define _TRANS_VTOTAL_B 0x6100c
372#define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
373#define VTOTAL_MASK REG_GENMASK(31, 16)
374#define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal))
375#define VACTIVE_MASK REG_GENMASK(15, 0)
376#define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay))
377
378#define _TRANS_VBLANK_A 0x60010
379#define _TRANS_VBLANK_B 0x61010
380#define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
381#define VBLANK_END_MASK REG_GENMASK(31, 16)
382#define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end))
383#define VBLANK_START_MASK REG_GENMASK(15, 0)
384#define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start))
385
386#define _TRANS_VSYNC_A 0x60014
387#define _TRANS_VSYNC_B 0x61014
388#define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
389#define VSYNC_END_MASK REG_GENMASK(31, 16)
390#define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
391#define VSYNC_START_MASK REG_GENMASK(15, 0)
392#define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
393
394#define _PIPEASRC 0x6001c
395#define _PIPEBSRC 0x6101c
396#define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
397#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
398#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
399#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
400#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
401
402#define _BCLRPAT_A 0x60020
403#define _BCLRPAT_B 0x61020
404#define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
405
406#define _TRANS_VSYNCSHIFT_A 0x60028
407#define _TRANS_VSYNCSHIFT_B 0x61028
408#define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
409
410#define _TRANS_MULT_A 0x6002c
411#define _TRANS_MULT_B 0x6102c
412#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
413
414/* Hotplug control (945+ only) */
415#define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
416#define PORTB_HOTPLUG_INT_EN (1 << 29)
417#define PORTC_HOTPLUG_INT_EN (1 << 28)
418#define PORTD_HOTPLUG_INT_EN (1 << 27)
419#define SDVOB_HOTPLUG_INT_EN (1 << 26)
420#define SDVOC_HOTPLUG_INT_EN (1 << 25)
421#define TV_HOTPLUG_INT_EN (1 << 18)
422#define CRT_HOTPLUG_INT_EN (1 << 9)
423#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
424 PORTC_HOTPLUG_INT_EN | \
425 PORTD_HOTPLUG_INT_EN | \
426 SDVOC_HOTPLUG_INT_EN | \
427 SDVOB_HOTPLUG_INT_EN | \
428 CRT_HOTPLUG_INT_EN)
429#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
430#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
431/* must use period 64 on GM45 according to docs */
432#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
433#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
434#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
435#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
436#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
437#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
438#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
439#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
440#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
441#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
442#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
443#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
444
445#define PORT_HOTPLUG_STAT(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
446/* HDMI/DP bits are g4x+ */
447#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
448#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
449#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
450#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
451#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
452#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
453#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
454#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
455#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
456#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
457#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
458#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
459/* CRT/TV common between gen3+ */
460#define CRT_HOTPLUG_INT_STATUS (1 << 11)
461#define TV_HOTPLUG_INT_STATUS (1 << 10)
462#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
463#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
464#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
465#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
466#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
467#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
468#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
469#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
470
471/* SDVO is different across gen3/4 */
472#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
473#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
474/*
475 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
476 * since reality corrobates that they're the same as on gen3. But keep these
477 * bits here (and the comment!) to help any other lost wanderers back onto the
478 * right tracks.
479 */
480#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
481#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
482#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
483#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
484#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
485 SDVOB_HOTPLUG_INT_STATUS_G4X | \
486 SDVOC_HOTPLUG_INT_STATUS_G4X | \
487 PORTB_HOTPLUG_INT_STATUS | \
488 PORTC_HOTPLUG_INT_STATUS | \
489 PORTD_HOTPLUG_INT_STATUS)
490
491#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
492 SDVOB_HOTPLUG_INT_STATUS_I915 | \
493 SDVOC_HOTPLUG_INT_STATUS_I915 | \
494 PORTB_HOTPLUG_INT_STATUS | \
495 PORTC_HOTPLUG_INT_STATUS | \
496 PORTD_HOTPLUG_INT_STATUS)
497
498/* SDVO and HDMI port control.
499 * The same register may be used for SDVO or HDMI */
500#define _GEN3_SDVOB 0x61140
501#define _GEN3_SDVOC 0x61160
502#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
503#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
504#define GEN4_HDMIB GEN3_SDVOB
505#define GEN4_HDMIC GEN3_SDVOC
506#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
507#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
508#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
509#define PCH_SDVOB _MMIO(0xe1140)
510#define PCH_HDMIB PCH_SDVOB
511#define PCH_HDMIC _MMIO(0xe1150)
512#define PCH_HDMID _MMIO(0xe1160)
513
514#define PORT_DFT_I9XX _MMIO(0x61150)
515#define DC_BALANCE_RESET (1 << 25)
516#define PORT_DFT2_G4X(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
517#define DC_BALANCE_RESET_VLV (1 << 31)
518#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
519#define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
520#define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
521#define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
522
523/* Gen 3 SDVO bits: */
524#define SDVO_ENABLE (1 << 31)
525#define SDVO_PIPE_SEL_SHIFT 30
526#define SDVO_PIPE_SEL_MASK (1 << 30)
527#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
528#define SDVO_STALL_SELECT (1 << 29)
529#define SDVO_INTERRUPT_ENABLE (1 << 26)
530/*
531 * 915G/GM SDVO pixel multiplier.
532 * Programmed value is multiplier - 1, up to 5x.
533 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
534 */
535#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
536#define SDVO_PORT_MULTIPLY_SHIFT 23
537#define SDVO_PHASE_SELECT_MASK (15 << 19)
538#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
539#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
540#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
541#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
542#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
543#define SDVO_DETECTED (1 << 2)
544/* Bits to be preserved when writing */
545#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
546 SDVO_INTERRUPT_ENABLE)
547#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
548
549/* Gen 4 SDVO/HDMI bits: */
550#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
551#define SDVO_COLOR_FORMAT_MASK (7 << 26)
552#define SDVO_ENCODING_SDVO (0 << 10)
553#define SDVO_ENCODING_HDMI (2 << 10)
554#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
555#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
556#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
557#define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */
558/* VSYNC/HSYNC bits new with 965, default is to be set */
559#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
560#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
561
562/* Gen 5 (IBX) SDVO/HDMI bits: */
563#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
564#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
565
566/* Gen 6 (CPT) SDVO/HDMI bits: */
567#define SDVO_PIPE_SEL_SHIFT_CPT 29
568#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
569#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
570
571/* CHV SDVO/HDMI bits: */
572#define SDVO_PIPE_SEL_SHIFT_CHV 24
573#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
574#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
575
576/* Video Data Island Packet control */
577#define VIDEO_DIP_DATA _MMIO(0x61178)
578/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
579 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
580 * of the infoframe structure specified by CEA-861. */
581#define VIDEO_DIP_DATA_SIZE 32
582#define VIDEO_DIP_ASYNC_DATA_SIZE 36
583#define VIDEO_DIP_GMP_DATA_SIZE 36
584#define VIDEO_DIP_VSC_DATA_SIZE 36
585#define VIDEO_DIP_PPS_DATA_SIZE 132
586#define VIDEO_DIP_CTL _MMIO(0x61170)
587/* Pre HSW: */
588#define VIDEO_DIP_ENABLE (1 << 31)
589#define VIDEO_DIP_PORT(port) ((port) << 29)
590#define VIDEO_DIP_PORT_MASK (3 << 29)
591#define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
592#define VIDEO_DIP_ENABLE_AVI (1 << 21)
593#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
594#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
595#define VIDEO_DIP_ENABLE_SPD (8 << 21)
596#define VIDEO_DIP_SELECT_AVI (0 << 19)
597#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
598#define VIDEO_DIP_SELECT_GAMUT (2 << 19)
599#define VIDEO_DIP_SELECT_SPD (3 << 19)
600#define VIDEO_DIP_SELECT_MASK (3 << 19)
601#define VIDEO_DIP_FREQ_ONCE (0 << 16)
602#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
603#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
604#define VIDEO_DIP_FREQ_MASK (3 << 16)
605/* HSW and later: */
606#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
607#define PSR_VSC_BIT_7_SET (1 << 27)
608#define VSC_SELECT_MASK (0x3 << 25)
609#define VSC_SELECT_SHIFT 25
610#define VSC_DIP_HW_HEA_DATA (0 << 25)
611#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
612#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
613#define VSC_DIP_SW_HEA_DATA (3 << 25)
614#define VDIP_ENABLE_PPS (1 << 24)
615#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
616#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
617#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
618#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
619#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
620#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
621/* ADL and later: */
622#define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23)
623
624#define PCH_GTC_CTL _MMIO(0xe7000)
625#define PCH_GTC_ENABLE (1 << 31)
626
627/* Display Port */
628#define DP_A _MMIO(0x64000) /* eDP */
629#define DP_B _MMIO(0x64100)
630#define DP_C _MMIO(0x64200)
631#define DP_D _MMIO(0x64300)
632#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
633#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
634#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
635#define DP_PORT_EN REG_BIT(31)
636#define DP_PIPE_SEL_MASK REG_GENMASK(30, 30)
637#define DP_PIPE_SEL(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK, (pipe))
638#define DP_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29)
639#define DP_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK_IVB, (pipe))
640#define DP_PIPE_SEL_SHIFT_CHV 16
641#define DP_PIPE_SEL_MASK_CHV REG_GENMASK(17, 16)
642#define DP_PIPE_SEL_CHV(pipe) REG_FIELD_PREP(DP_PIPE_SEL_MASK_CHV, (pipe))
643#define DP_LINK_TRAIN_MASK REG_GENMASK(29, 28)
644#define DP_LINK_TRAIN_PAT_1 REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 0)
645#define DP_LINK_TRAIN_PAT_2 REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 1)
646#define DP_LINK_TRAIN_PAT_IDLE REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 2)
647#define DP_LINK_TRAIN_OFF REG_FIELD_PREP(DP_LINK_TRAIN_MASK, 3)
648#define DP_LINK_TRAIN_MASK_CPT REG_GENMASK(10, 8)
649#define DP_LINK_TRAIN_PAT_1_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 0)
650#define DP_LINK_TRAIN_PAT_2_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 1)
651#define DP_LINK_TRAIN_PAT_IDLE_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 2)
652#define DP_LINK_TRAIN_OFF_CPT REG_FIELD_PREP(DP_LINK_TRAIN_MASK_CPT, 3)
653#define DP_VOLTAGE_MASK REG_GENMASK(27, 25)
654#define DP_VOLTAGE_0_4 REG_FIELD_PREP(DP_VOLTAGE_MASK, 0)
655#define DP_VOLTAGE_0_6 REG_FIELD_PREP(DP_VOLTAGE_MASK, 1)
656#define DP_VOLTAGE_0_8 REG_FIELD_PREP(DP_VOLTAGE_MASK, 2)
657#define DP_VOLTAGE_1_2 REG_FIELD_PREP(DP_VOLTAGE_MASK, 3)
658#define DP_PRE_EMPHASIS_MASK REG_GENMASK(24, 22)
659#define DP_PRE_EMPHASIS_0 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 0)
660#define DP_PRE_EMPHASIS_3_5 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 1)
661#define DP_PRE_EMPHASIS_6 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 2)
662#define DP_PRE_EMPHASIS_9_5 REG_FIELD_PREP(DP_PRE_EMPHASIS_MASK, 3)
663#define DP_PORT_WIDTH_MASK REG_GENMASK(21, 19)
664#define DP_PORT_WIDTH(width) REG_FIELD_PREP(DP_PORT_WIDTH_MASK, (width) - 1)
665#define DP_ENHANCED_FRAMING REG_BIT(18)
666#define EDP_PLL_FREQ_MASK REG_GENMASK(17, 16)
667#define EDP_PLL_FREQ_270MHZ REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 0)
668#define EDP_PLL_FREQ_162MHZ REG_FIELD_PREP(EDP_PLL_FREQ_MASK, 1)
669#define DP_PORT_REVERSAL REG_BIT(15)
670#define EDP_PLL_ENABLE REG_BIT(14)
671#define DP_CLOCK_OUTPUT_ENABLE REG_BIT(13)
672#define DP_SCRAMBLING_DISABLE REG_BIT(12)
673#define DP_SCRAMBLING_DISABLE_ILK REG_BIT(7)
674#define DP_COLOR_RANGE_16_235 REG_BIT(8)
675#define DP_AUDIO_OUTPUT_ENABLE REG_BIT(6)
676#define DP_SYNC_VS_HIGH REG_BIT(4)
677#define DP_SYNC_HS_HIGH REG_BIT(3)
678#define DP_DETECTED REG_BIT(2)
679
680/*
681 * Computing GMCH M and N values for the Display Port link
682 *
683 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
684 *
685 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
686 *
687 * The GMCH value is used internally
688 *
689 * bytes_per_pixel is the number of bytes coming out of the plane,
690 * which is after the LUTs, so we want the bytes for our color format.
691 * For our current usage, this is always 3, one byte for R, G and B.
692 */
693#define _PIPEA_DATA_M_G4X 0x70050
694#define _PIPEB_DATA_M_G4X 0x71050
695#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
696/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
697#define TU_SIZE_MASK REG_GENMASK(30, 25)
698#define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
699#define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
700#define DATA_LINK_N_MAX (0x800000)
701
702#define _PIPEA_DATA_N_G4X 0x70054
703#define _PIPEB_DATA_N_G4X 0x71054
704#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
705
706/*
707 * Computing Link M and N values for the Display Port link
708 *
709 * Link M / N = pixel_clock / ls_clk
710 *
711 * (the DP spec calls pixel_clock the 'strm_clk')
712 *
713 * The Link value is transmitted in the Main Stream
714 * Attributes and VB-ID.
715 */
716#define _PIPEA_LINK_M_G4X 0x70060
717#define _PIPEB_LINK_M_G4X 0x71060
718#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
719
720#define _PIPEA_LINK_N_G4X 0x70064
721#define _PIPEB_LINK_N_G4X 0x71064
722#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
723
724/* Pipe A */
725#define _PIPEADSL 0x70000
726#define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
727#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
728#define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
729
730#define _TRANSACONF 0x70008
731#define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
732#define TRANSCONF_ENABLE REG_BIT(31)
733#define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
734#define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */
735#define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
736#define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
737#define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
738#define TRANSCONF_PIPE_LOCKED REG_BIT(25)
739#define TRANSCONF_FORCE_BORDER REG_BIT(25)
740#define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
741#define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
742#define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)
743#define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1)
744#define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
745#define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
746#define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
747#define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
748#define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)
749#define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */
750#define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */
751#define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6)
752#define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */
753/*
754 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
755 * DBL=power saving pixel doubling, PF-ID* requires panel fitter
756 */
757#define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
758#define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
759#define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)
760#define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1)
761#define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3)
762#define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
763#define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
764#define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
765#define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
766#define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
767#define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
768#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */
769#define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
770#define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
771#define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
772#define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
773#define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
774#define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
775#define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
776#define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
777#define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)
778#define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1)
779#define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2)
780#define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3)
781#define TRANSCONF_DITHER_EN REG_BIT(4)
782#define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
783#define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)
784#define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)
785#define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)
786#define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
787#define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0)
788#define TRANSCONF_PIXEL_COUNT_SCALING_X4 1
789
790#define _PIPEASTAT 0x70024
791#define PIPESTAT(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
792#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
793#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
794#define PIPE_CRC_ERROR_ENABLE (1UL << 29)
795#define PIPE_CRC_DONE_ENABLE (1UL << 28)
796#define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
797#define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
798#define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
799#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
800#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
801#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
802#define PIPE_DPST_EVENT_ENABLE (1UL << 23)
803#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22)
804#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
805#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)
806#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)
807#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19)
808#define PERF_COUNTER_INTERRUPT_EN (1UL << 19)
809#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
810#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */
811#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17)
812#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
813#define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)
814#define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)
815#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15)
816#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14)
817#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)
818#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)
819#define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11)
820#define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)
821#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10)
822#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
823#define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)
824#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)
825#define PIPE_DPST_EVENT_STATUS (1UL << 7)
826#define PIPE_A_PSR_STATUS_VLV (1UL << 6)
827#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)
828#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)
829#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)
830#define PIPE_B_PSR_STATUS_VLV (1UL << 3)
831#define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3)
832#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
833#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */
834#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1)
835#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
836#define PIPE_HBLANK_INT_STATUS (1UL << 0)
837#define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
838#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
839#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
840
841#define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
842#define PIPE_ARB_CTL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)
843#define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
844
845#define _PIPE_MISC_A 0x70030
846#define _PIPE_MISC_B 0x71030
847#define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)
848#define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
849#define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
850#define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
851#define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */
852#define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */
853#define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */
854#define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */
855#define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20)
856#define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
857#define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
858/*
859 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
860 * valid values of: 6, 8, 10 BPC.
861 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
862 * 6, 8, 10, 12 BPC.
863 */
864#define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5)
865#define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0)
866#define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1)
867#define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2)
868#define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */
869#define PIPE_MISC_DITHER_ENABLE REG_BIT(4)
870#define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
871#define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0)
872#define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1)
873#define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2)
874#define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3)
875
876#define _PIPE_MISC2_A 0x7002C
877#define _PIPE_MISC2_B 0x7102C
878#define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)
879#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
880#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
881#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
882#define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
883#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
884
885#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
886#define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16)
887#define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16)
888#define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
889#define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
890#define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
891#define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
892#define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
893#define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
894#define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
895#define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
896#define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
897#define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
898#define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
899#define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
900#define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
901#define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
902#define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
903#define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
904#define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
905#define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
906#define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
907#define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
908#define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
909#define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
910#define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
911#define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
912#define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
913#define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
914
915#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
916#define CBR_PND_DEADLINE_DISABLE (1 << 31)
917#define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
918
919#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
920#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
921
922/*
923 * The two pipe frame counter registers are not synchronized, so
924 * reading a stable value is somewhat tricky. The following code
925 * should work:
926 *
927 * do {
928 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
929 * PIPE_FRAME_HIGH_SHIFT;
930 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
931 * PIPE_FRAME_LOW_SHIFT);
932 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
933 * PIPE_FRAME_HIGH_SHIFT);
934 * } while (high1 != high2);
935 * frame = (high1 << 8) | low1;
936 */
937#define _PIPEAFRAMEHIGH 0x70040
938#define PIPEFRAME(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
939#define PIPE_FRAME_HIGH_MASK 0x0000ffff
940#define PIPE_FRAME_HIGH_SHIFT 0
941
942#define _PIPEAFRAMEPIXEL 0x70044
943#define PIPEFRAMEPIXEL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
944#define PIPE_FRAME_LOW_MASK 0xff000000
945#define PIPE_FRAME_LOW_SHIFT 24
946#define PIPE_PIXEL_MASK 0x00ffffff
947#define PIPE_PIXEL_SHIFT 0
948
949/* GM45+ just has to be different */
950#define _PIPEA_FRMCOUNT_G4X 0x70040
951#define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
952
953#define _PIPEA_FLIPCOUNT_G4X 0x70044
954#define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
955
956/* CHV pipe B blender */
957#define _CHV_BLEND_A 0x60a00
958#define CHV_BLEND(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)
959#define CHV_BLEND_MASK REG_GENMASK(31, 30)
960#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
961#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)
962#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
963
964#define _CHV_CANVAS_A 0x60a04
965#define CHV_CANVAS(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)
966#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
967#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
968#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
969
970/* Display/Sprite base address macros */
971#define DISP_BASEADDR_MASK (0xfffff000)
972#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
973#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
974
975/*
976 * VBIOS flags
977 * gen2:
978 * [00:06] alm,mgm
979 * [10:16] all
980 * [30:32] alm,mgm
981 * gen3+:
982 * [00:0f] all
983 * [10:1f] all
984 * [30:32] all
985 */
986#define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
987#define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
988#define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
989#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
990
991#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
992#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
993#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
994#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
995#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
996#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
997#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
998#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
999#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
1000#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
1001#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
1002
1003/* refresh rate hardware control */
1004#define RR_HW_CTL _MMIO(0x45300)
1005#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
1006#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
1007
1008#define _PIPEA_DATA_M1 0x60030
1009#define _PIPEB_DATA_M1 0x61030
1010#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
1011
1012#define _PIPEA_DATA_N1 0x60034
1013#define _PIPEB_DATA_N1 0x61034
1014#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
1015
1016#define _PIPEA_DATA_M2 0x60038
1017#define _PIPEB_DATA_M2 0x61038
1018#define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
1019
1020#define _PIPEA_DATA_N2 0x6003c
1021#define _PIPEB_DATA_N2 0x6103c
1022#define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
1023
1024#define _PIPEA_LINK_M1 0x60040
1025#define _PIPEB_LINK_M1 0x61040
1026#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
1027
1028#define _PIPEA_LINK_N1 0x60044
1029#define _PIPEB_LINK_N1 0x61044
1030#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
1031
1032#define _PIPEA_LINK_M2 0x60048
1033#define _PIPEB_LINK_M2 0x61048
1034#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
1035
1036#define _PIPEA_LINK_N2 0x6004c
1037#define _PIPEB_LINK_N2 0x6104c
1038#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
1039
1040/*
1041 * Skylake scalers
1042 */
1043#define _ID(id, a, b) _PICK_EVEN(id, a, b)
1044#define _PS_1A_CTRL 0x68180
1045#define _PS_2A_CTRL 0x68280
1046#define _PS_1B_CTRL 0x68980
1047#define _PS_2B_CTRL 0x68A80
1048#define _PS_1C_CTRL 0x69180
1049#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
1050 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
1051 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
1052#define PS_SCALER_EN REG_BIT(31)
1053#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
1054#define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
1055#define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
1056#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
1057#define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
1058#define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
1059#define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2)
1060#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
1061#define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
1062#define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
1063#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
1064#define PS_BINDING_MASK REG_GENMASK(27, 25)
1065#define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
1066#define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
1067#define PS_FILTER_MASK REG_GENMASK(24, 23)
1068#define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0)
1069#define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
1070#define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
1071#define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
1072#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
1073#define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
1074#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
1075#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
1076#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
1077#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
1078#define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
1079#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
1080#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
1081#define PS_PWRUP_PROGRESS REG_BIT(17)
1082#define PS_V_FILTER_BYPASS REG_BIT(8)
1083#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
1084#define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */
1085#define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)
1086#define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1)
1087#define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3)
1088#define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
1089#define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1)
1090#define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */
1091#define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set))
1092#define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */
1093#define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set))
1094#define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */
1095#define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set))
1096#define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */
1097#define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set))
1098
1099#define _PS_PWR_GATE_1A 0x68160
1100#define _PS_PWR_GATE_2A 0x68260
1101#define _PS_PWR_GATE_1B 0x68960
1102#define _PS_PWR_GATE_2B 0x68A60
1103#define _PS_PWR_GATE_1C 0x69160
1104#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
1105 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
1106 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
1107#define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31)
1108#define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3)
1109#define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
1110#define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1)
1111#define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2)
1112#define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3)
1113#define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
1114#define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)
1115#define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1)
1116#define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2)
1117#define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3)
1118
1119#define _PS_WIN_POS_1A 0x68170
1120#define _PS_WIN_POS_2A 0x68270
1121#define _PS_WIN_POS_1B 0x68970
1122#define _PS_WIN_POS_2B 0x68A70
1123#define _PS_WIN_POS_1C 0x69170
1124#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
1125 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
1126 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
1127#define PS_WIN_XPOS_MASK REG_GENMASK(31, 16)
1128#define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x))
1129#define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
1130#define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y))
1131
1132#define _PS_WIN_SZ_1A 0x68174
1133#define _PS_WIN_SZ_2A 0x68274
1134#define _PS_WIN_SZ_1B 0x68974
1135#define _PS_WIN_SZ_2B 0x68A74
1136#define _PS_WIN_SZ_1C 0x69174
1137#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
1138 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
1139 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
1140#define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16)
1141#define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w))
1142#define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
1143#define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h))
1144
1145#define _PS_VSCALE_1A 0x68184
1146#define _PS_VSCALE_2A 0x68284
1147#define _PS_VSCALE_1B 0x68984
1148#define _PS_VSCALE_2B 0x68A84
1149#define _PS_VSCALE_1C 0x69184
1150#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
1151 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
1152 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
1153
1154#define _PS_HSCALE_1A 0x68190
1155#define _PS_HSCALE_2A 0x68290
1156#define _PS_HSCALE_1B 0x68990
1157#define _PS_HSCALE_2B 0x68A90
1158#define _PS_HSCALE_1C 0x69190
1159#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
1160 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
1161 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
1162
1163#define _PS_VPHASE_1A 0x68188
1164#define _PS_VPHASE_2A 0x68288
1165#define _PS_VPHASE_1B 0x68988
1166#define _PS_VPHASE_2B 0x68A88
1167#define _PS_VPHASE_1C 0x69188
1168#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
1169 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
1170 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
1171#define PS_Y_PHASE_MASK REG_GENMASK(31, 16)
1172#define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x))
1173#define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
1174#define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x))
1175#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
1176#define PS_PHASE_TRIP (1 << 0)
1177
1178#define _PS_HPHASE_1A 0x68194
1179#define _PS_HPHASE_2A 0x68294
1180#define _PS_HPHASE_1B 0x68994
1181#define _PS_HPHASE_2B 0x68A94
1182#define _PS_HPHASE_1C 0x69194
1183#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
1184 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
1185 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
1186
1187#define _PS_ECC_STAT_1A 0x681D0
1188#define _PS_ECC_STAT_2A 0x682D0
1189#define _PS_ECC_STAT_1B 0x689D0
1190#define _PS_ECC_STAT_2B 0x68AD0
1191#define _PS_ECC_STAT_1C 0x691D0
1192#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
1193 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
1194 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
1195
1196#define _PS_COEF_SET0_INDEX_1A 0x68198
1197#define _PS_COEF_SET0_INDEX_2A 0x68298
1198#define _PS_COEF_SET0_INDEX_1B 0x68998
1199#define _PS_COEF_SET0_INDEX_2B 0x68A98
1200#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
1201 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
1202 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
1203#define PS_COEF_INDEX_AUTO_INC REG_BIT(10)
1204
1205#define _PS_COEF_SET0_DATA_1A 0x6819C
1206#define _PS_COEF_SET0_DATA_2A 0x6829C
1207#define _PS_COEF_SET0_DATA_1B 0x6899C
1208#define _PS_COEF_SET0_DATA_2B 0x68A9C
1209#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
1210 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
1211 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
1212
1213/* More Ivybridge lolz */
1214#define DE_ERR_INT_IVB (1 << 30)
1215#define DE_GSE_IVB (1 << 29)
1216#define DE_PCH_EVENT_IVB (1 << 28)
1217#define DE_DP_A_HOTPLUG_IVB (1 << 27)
1218#define DE_AUX_CHANNEL_A_IVB (1 << 26)
1219#define DE_EDP_PSR_INT_HSW (1 << 19)
1220#define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
1221#define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
1222#define DE_PIPEC_VBLANK_IVB (1 << 10)
1223#define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
1224#define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
1225#define DE_PIPEB_VBLANK_IVB (1 << 5)
1226#define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
1227#define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
1228#define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
1229#define DE_PIPEA_VBLANK_IVB (1 << 0)
1230#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
1231
1232#define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
1233
1234#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
1235#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
1236#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
1237#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
1238#define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31)
1239#define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29)
1240#define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28)
1241#define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
1242#define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl-mtl */
1243#define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl */
1244#define GEN12_PIPEDMC_FLIPQ_DONE REG_BIT(24) /* tgl-adl */
1245#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
1246#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */
1247#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */
1248#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */
1249#define MTL_PLANE_ATS_FAULT REG_BIT(18) /* mtl+ */
1250#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */
1251#define MTL_PIPEDMC_FLIPQ_DONE REG_BIT(17) /* mtl */
1252#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */
1253#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */
1254#define GEN12_DSB_2_INT REG_BIT(15) /* tgl+ */
1255#define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */
1256#define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */
1257#define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id))
1258#define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */
1259#define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */
1260#define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */
1261#define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) /* skl+ */
1262#define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) /* bdw */
1263#define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) /* skl+ */
1264#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */
1265#define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) /* skl+ */
1266#define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) /* skl+ */
1267#define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) /* skl+ */
1268#define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) /* bdw */
1269#define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */
1270#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */
1271#define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */
1272#define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \
1273 REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */
1274#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2)
1275#define GEN8_PIPE_VSYNC REG_BIT(1)
1276#define GEN8_PIPE_VBLANK REG_BIT(0)
1277
1278#define GEN8_DE_PIPE_IRQ_REGS(pipe) I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \
1279 GEN8_DE_PIPE_IER(pipe), \
1280 GEN8_DE_PIPE_IIR(pipe))
1281
1282#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
1283#define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
1284
1285#define GEN8_DE_PORT_ISR _MMIO(0x44440)
1286#define GEN8_DE_PORT_IMR _MMIO(0x44444)
1287#define GEN8_DE_PORT_IIR _MMIO(0x44448)
1288#define GEN8_DE_PORT_IER _MMIO(0x4444c)
1289#define DSI1_NON_TE (1 << 31)
1290#define DSI0_NON_TE (1 << 30)
1291#define ICL_AUX_CHANNEL_E (1 << 29)
1292#define ICL_AUX_CHANNEL_F (1 << 28)
1293#define GEN9_AUX_CHANNEL_D (1 << 27)
1294#define GEN9_AUX_CHANNEL_C (1 << 26)
1295#define GEN9_AUX_CHANNEL_B (1 << 25)
1296#define DSI1_TE (1 << 24)
1297#define DSI0_TE (1 << 23)
1298#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
1299#define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
1300 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
1301 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
1302#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
1303#define BXT_DE_PORT_GMBUS (1 << 1)
1304#define GEN8_AUX_CHANNEL_A (1 << 0)
1305#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
1306#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
1307#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
1308#define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
1309#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
1310#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
1311#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
1312#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
1313#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
1314#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
1315#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
1316
1317#define GEN8_DE_PORT_IRQ_REGS I915_IRQ_REGS(GEN8_DE_PORT_IMR, \
1318 GEN8_DE_PORT_IER, \
1319 GEN8_DE_PORT_IIR)
1320
1321#define GEN8_DE_MISC_ISR _MMIO(0x44460)
1322#define GEN8_DE_MISC_IMR _MMIO(0x44464)
1323#define GEN8_DE_MISC_IIR _MMIO(0x44468)
1324#define GEN8_DE_MISC_IER _MMIO(0x4446c)
1325#define XELPDP_RM_TIMEOUT REG_BIT(29)
1326#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
1327#define GEN8_DE_MISC_GSE REG_BIT(27)
1328#define GEN8_DE_EDP_PSR REG_BIT(19)
1329#define XELPDP_PMDEMAND_RSP REG_BIT(3)
1330#define XE2LPD_DBUF_OVERLAP_DETECTED REG_BIT(1)
1331
1332#define GEN8_DE_MISC_IRQ_REGS I915_IRQ_REGS(GEN8_DE_MISC_IMR, \
1333 GEN8_DE_MISC_IER, \
1334 GEN8_DE_MISC_IIR)
1335
1336#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
1337#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
1338#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
1339#define GEN11_DE_PCH_IRQ (1 << 23)
1340#define GEN11_DE_MISC_IRQ (1 << 22)
1341#define GEN11_DE_HPD_IRQ (1 << 21)
1342#define GEN11_DE_PORT_IRQ (1 << 20)
1343#define GEN11_DE_PIPE_C (1 << 18)
1344#define GEN11_DE_PIPE_B (1 << 17)
1345#define GEN11_DE_PIPE_A (1 << 16)
1346
1347#define GEN11_DE_HPD_ISR _MMIO(0x44470)
1348#define GEN11_DE_HPD_IMR _MMIO(0x44474)
1349#define GEN11_DE_HPD_IIR _MMIO(0x44478)
1350#define GEN11_DE_HPD_IER _MMIO(0x4447c)
1351#define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
1352#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
1353 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
1354 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
1355 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
1356 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
1357 GEN11_TC_HOTPLUG(HPD_PORT_TC1))
1358#define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
1359#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
1360 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
1361 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
1362 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
1363 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
1364 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
1365
1366#define GEN11_DE_HPD_IRQ_REGS I915_IRQ_REGS(GEN11_DE_HPD_IMR, \
1367 GEN11_DE_HPD_IER, \
1368 GEN11_DE_HPD_IIR)
1369
1370#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
1371#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
1372#define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
1373#define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
1374#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
1375#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
1376
1377#define PICAINTERRUPT_ISR _MMIO(0x16FE50)
1378#define PICAINTERRUPT_IMR _MMIO(0x16FE54)
1379#define PICAINTERRUPT_IIR _MMIO(0x16FE58)
1380#define PICAINTERRUPT_IER _MMIO(0x16FE5C)
1381#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
1382#define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16)
1383#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
1384#define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
1385#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
1386#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
1387#define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
1388#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
1389
1390#define PICAINTERRUPT_IRQ_REGS I915_IRQ_REGS(PICAINTERRUPT_IMR, \
1391 PICAINTERRUPT_IER, \
1392 PICAINTERRUPT_IIR)
1393
1394#define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200))
1395#define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6)
1396#define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5)
1397#define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4)
1398#define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2)
1399#define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
1400#define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
1401
1402#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))
1403#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16)
1404#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12)
1405#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8)
1406#define XE3_PMDEMAND_PIPES_MASK REG_GENMASK(7, 4)
1407#define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6)
1408#define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4)
1409#define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
1410
1411#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
1412#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20)
1413#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8)
1414#define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4)
1415#define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0)
1416
1417#define GEN12_DCPR_STATUS_1 _MMIO(0x46440)
1418#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
1419
1420#define FUSE_STRAP _MMIO(0x42014)
1421#define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31)
1422#define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30)
1423#define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29)
1424#define IVB_PIPE_C_DISABLE REG_BIT(28)
1425#define ILK_HDCP_DISABLE REG_BIT(25)
1426#define ILK_eDP_A_DISABLE REG_BIT(24)
1427#define HSW_CDCLK_LIMIT REG_BIT(24)
1428#define ILK_DESKTOP REG_BIT(23)
1429#define HSW_CPU_SSC_ENABLE REG_BIT(21)
1430
1431#define FUSE_STRAP3 _MMIO(0x42020)
1432#define HSW_REF_CLK_SELECT REG_BIT(1)
1433
1434#define CHICKEN_MISC_2 _MMIO(0x42084)
1435#define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */
1436#define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27)
1437#define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
1438#define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
1439#define GLK_CL2_PWR_DOWN REG_BIT(12)
1440#define GLK_CL1_PWR_DOWN REG_BIT(11)
1441#define GLK_CL0_PWR_DOWN REG_BIT(10)
1442
1443#define CHICKEN_MISC_3 _MMIO(0x42088)
1444#define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A)
1445#define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
1446#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
1447
1448#define CHICKEN_MISC_4 _MMIO(0x4208c)
1449#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
1450#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
1451#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
1452
1453#define _CHICKEN_TRANS_A 0x420c0
1454#define _CHICKEN_TRANS_B 0x420c4
1455#define _CHICKEN_TRANS_C 0x420c8
1456#define _CHICKEN_TRANS_EDP 0x420cc
1457#define _CHICKEN_TRANS_D 0x420d8
1458#define _CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
1459 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
1460 [TRANSCODER_A] = _CHICKEN_TRANS_A, \
1461 [TRANSCODER_B] = _CHICKEN_TRANS_B, \
1462 [TRANSCODER_C] = _CHICKEN_TRANS_C, \
1463 [TRANSCODER_D] = _CHICKEN_TRANS_D))
1464#define _MTL_CHICKEN_TRANS_A 0x604e0
1465#define _MTL_CHICKEN_TRANS_B 0x614e0
1466#define _MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \
1467 _MTL_CHICKEN_TRANS_A, \
1468 _MTL_CHICKEN_TRANS_B)
1469#define CHICKEN_TRANS(display, trans) (DISPLAY_VER(display) >= 14 ? _MTL_CHICKEN_TRANS(trans) : _CHICKEN_TRANS(trans))
1470#define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */
1471#define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */
1472#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
1473#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
1474#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
1475#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
1476#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
1477#define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
1478#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
1479#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
1480#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
1481#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
1482#define DP_FEC_BS_JITTER_WA REG_BIT(15)
1483#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
1484#define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
1485#define HDCP_LINE_REKEY_DISABLE REG_BIT(0)
1486
1487#define DISP_ARB_CTL2 _MMIO(0x45004)
1488#define DISP_DATA_PARTITION_5_6 REG_BIT(6)
1489#define DISP_IPC_ENABLE REG_BIT(3)
1490
1491#define GEN7_MSG_CTL _MMIO(0x45010)
1492#define WAIT_FOR_PCH_RESET_ACK (1 << 1)
1493#define WAIT_FOR_PCH_FLR_ACK (1 << 0)
1494
1495#define _BW_BUDDY0_CTL 0x45130
1496#define _BW_BUDDY1_CTL 0x45140
1497#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
1498 _BW_BUDDY0_CTL, \
1499 _BW_BUDDY1_CTL))
1500#define BW_BUDDY_DISABLE REG_BIT(31)
1501#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
1502#define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
1503
1504#define _BW_BUDDY0_PAGE_MASK 0x45134
1505#define _BW_BUDDY1_PAGE_MASK 0x45144
1506#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
1507 _BW_BUDDY0_PAGE_MASK, \
1508 _BW_BUDDY1_PAGE_MASK))
1509
1510#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
1511#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
1512#define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
1513
1514#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
1515#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
1516#define DCPR_MASK_LPMODE REG_BIT(26)
1517#define DCPR_SEND_RESP_IMM REG_BIT(25)
1518#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
1519
1520#define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)
1521#define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19)
1522
1523#define SKL_DFSM _MMIO(0x51000)
1524#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
1525#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
1526#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
1527#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
1528#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
1529#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
1530#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
1531#define ICL_DFSM_DMC_DISABLE (1 << 23)
1532#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
1533#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
1534#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
1535#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
1536#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
1537#define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3)
1538
1539#define XE2LPD_DE_CAP _MMIO(0x41100)
1540#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
1541#define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28)
1542#define XE2LPD_DE_CAP_DSC_REMOVED 1
1543#define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26)
1544#define XE2LPD_DE_CAP_SCALER_SINGLE 1
1545
1546#define SKL_DSSM _MMIO(0x51004)
1547#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
1548#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
1549#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
1550#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
1551
1552/*GEN11 chicken */
1553#define _PIPEA_CHICKEN 0x70038
1554#define _PIPEB_CHICKEN 0x71038
1555#define _PIPEC_CHICKEN 0x72038
1556#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
1557 _PIPEB_CHICKEN)
1558#define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
1559#define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
1560#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
1561#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
1562#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
1563
1564#define PCH_DISPLAY_BASE 0xc0000u
1565
1566/* south display engine interrupt: IBX */
1567#define SDE_AUDIO_POWER_D (1 << 27)
1568#define SDE_AUDIO_POWER_C (1 << 26)
1569#define SDE_AUDIO_POWER_B (1 << 25)
1570#define SDE_AUDIO_POWER_SHIFT (25)
1571#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
1572#define SDE_GMBUS (1 << 24)
1573#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
1574#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
1575#define SDE_AUDIO_HDCP_MASK (3 << 22)
1576#define SDE_AUDIO_TRANSB (1 << 21)
1577#define SDE_AUDIO_TRANSA (1 << 20)
1578#define SDE_AUDIO_TRANS_MASK (3 << 20)
1579#define SDE_POISON (1 << 19)
1580/* 18 reserved */
1581#define SDE_FDI_RXB (1 << 17)
1582#define SDE_FDI_RXA (1 << 16)
1583#define SDE_FDI_MASK (3 << 16)
1584#define SDE_AUXD (1 << 15)
1585#define SDE_AUXC (1 << 14)
1586#define SDE_AUXB (1 << 13)
1587#define SDE_AUX_MASK (7 << 13)
1588/* 12 reserved */
1589#define SDE_CRT_HOTPLUG (1 << 11)
1590#define SDE_PORTD_HOTPLUG (1 << 10)
1591#define SDE_PORTC_HOTPLUG (1 << 9)
1592#define SDE_PORTB_HOTPLUG (1 << 8)
1593#define SDE_SDVOB_HOTPLUG (1 << 6)
1594#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
1595 SDE_SDVOB_HOTPLUG | \
1596 SDE_PORTB_HOTPLUG | \
1597 SDE_PORTC_HOTPLUG | \
1598 SDE_PORTD_HOTPLUG)
1599#define SDE_TRANSB_CRC_DONE (1 << 5)
1600#define SDE_TRANSB_CRC_ERR (1 << 4)
1601#define SDE_TRANSB_FIFO_UNDER (1 << 3)
1602#define SDE_TRANSA_CRC_DONE (1 << 2)
1603#define SDE_TRANSA_CRC_ERR (1 << 1)
1604#define SDE_TRANSA_FIFO_UNDER (1 << 0)
1605#define SDE_TRANS_MASK (0x3f)
1606
1607/* south display engine interrupt: CPT - CNP */
1608#define SDE_AUDIO_POWER_D_CPT (1 << 31)
1609#define SDE_AUDIO_POWER_C_CPT (1 << 30)
1610#define SDE_AUDIO_POWER_B_CPT (1 << 29)
1611#define SDE_AUDIO_POWER_SHIFT_CPT 29
1612#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
1613#define SDE_AUXD_CPT (1 << 27)
1614#define SDE_AUXC_CPT (1 << 26)
1615#define SDE_AUXB_CPT (1 << 25)
1616#define SDE_AUX_MASK_CPT (7 << 25)
1617#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
1618#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
1619#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
1620#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
1621#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
1622#define SDE_CRT_HOTPLUG_CPT (1 << 19)
1623#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
1624#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
1625 SDE_SDVOB_HOTPLUG_CPT | \
1626 SDE_PORTD_HOTPLUG_CPT | \
1627 SDE_PORTC_HOTPLUG_CPT | \
1628 SDE_PORTB_HOTPLUG_CPT)
1629#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
1630 SDE_PORTD_HOTPLUG_CPT | \
1631 SDE_PORTC_HOTPLUG_CPT | \
1632 SDE_PORTB_HOTPLUG_CPT | \
1633 SDE_PORTA_HOTPLUG_SPT)
1634#define SDE_GMBUS_CPT (1 << 17)
1635#define SDE_ERROR_CPT (1 << 16)
1636#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
1637#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
1638#define SDE_FDI_RXC_CPT (1 << 8)
1639#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
1640#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
1641#define SDE_FDI_RXB_CPT (1 << 4)
1642#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
1643#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
1644#define SDE_FDI_RXA_CPT (1 << 0)
1645#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
1646 SDE_AUDIO_CP_REQ_B_CPT | \
1647 SDE_AUDIO_CP_REQ_A_CPT)
1648#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
1649 SDE_AUDIO_CP_CHG_B_CPT | \
1650 SDE_AUDIO_CP_CHG_A_CPT)
1651#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
1652 SDE_FDI_RXB_CPT | \
1653 SDE_FDI_RXA_CPT)
1654
1655/* south display engine interrupt: ICP/TGP/MTP */
1656#define SDE_PICAINTERRUPT REG_BIT(31)
1657#define SDE_GMBUS_ICP (1 << 23)
1658#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
1659#define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
1660#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
1661#define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
1662 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
1663 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
1664 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
1665#define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
1666 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
1667 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
1668 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
1669 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
1670 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
1671
1672#define SDE_IRQ_REGS I915_IRQ_REGS(SDEIMR, \
1673 SDEIER, \
1674 SDEIIR)
1675
1676#define SERR_INT _MMIO(0xc4040)
1677#define SERR_INT_POISON (1 << 31)
1678#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
1679
1680/* digital port hotplug */
1681#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
1682#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
1683#define BXT_DDIA_HPD_INVERT (1 << 27)
1684#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
1685#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
1686#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
1687#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
1688#define PORTD_HOTPLUG_ENABLE (1 << 20)
1689#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
1690#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
1691#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
1692#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
1693#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
1694#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
1695#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
1696#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
1697#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
1698#define PORTC_HOTPLUG_ENABLE (1 << 12)
1699#define BXT_DDIC_HPD_INVERT (1 << 11)
1700#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
1701#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
1702#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
1703#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
1704#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
1705#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
1706#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
1707#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
1708#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
1709#define PORTB_HOTPLUG_ENABLE (1 << 4)
1710#define BXT_DDIB_HPD_INVERT (1 << 3)
1711#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
1712#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
1713#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
1714#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
1715#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
1716#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
1717#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
1718#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
1719#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
1720#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
1721 BXT_DDIB_HPD_INVERT | \
1722 BXT_DDIC_HPD_INVERT)
1723
1724#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
1725#define PORTE_HOTPLUG_ENABLE (1 << 4)
1726#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
1727#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
1728#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
1729#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
1730
1731/* This register is a reuse of PCH_PORT_HOTPLUG register. The
1732 * functionality covered in PCH_PORT_HOTPLUG is split into
1733 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
1734 */
1735#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
1736#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
1737#define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4))
1738#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
1739#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
1740#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
1741#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
1742#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
1743
1744#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
1745#define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
1746#define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
1747#define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
1748
1749#define SHPD_FILTER_CNT _MMIO(0xc4038)
1750#define SHPD_FILTER_CNT_500_ADJ 0x001D9
1751#define SHPD_FILTER_CNT_250 0x000F8
1752
1753#define _PCH_DPLL_A 0xc6014
1754#define _PCH_DPLL_B 0xc6018
1755#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
1756
1757#define _PCH_FPA0 0xc6040
1758#define _PCH_FPB0 0xc6048
1759#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
1760#define FP_CB_TUNE (0x3 << 22)
1761
1762#define _PCH_FPA1 0xc6044
1763#define _PCH_FPB1 0xc604c
1764#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
1765
1766#define PCH_DPLL_TEST _MMIO(0xc606c)
1767
1768#define PCH_DREF_CONTROL _MMIO(0xC6200)
1769#define DREF_CONTROL_MASK 0x7fc3
1770#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
1771#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
1772#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
1773#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
1774#define DREF_SSC_SOURCE_DISABLE (0 << 11)
1775#define DREF_SSC_SOURCE_ENABLE (2 << 11)
1776#define DREF_SSC_SOURCE_MASK (3 << 11)
1777#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
1778#define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
1779#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
1780#define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
1781#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
1782#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
1783#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
1784#define DREF_SSC4_DOWNSPREAD (0 << 6)
1785#define DREF_SSC4_CENTERSPREAD (1 << 6)
1786#define DREF_SSC1_DISABLE (0 << 1)
1787#define DREF_SSC1_ENABLE (1 << 1)
1788#define DREF_SSC4_DISABLE (0)
1789#define DREF_SSC4_ENABLE (1)
1790
1791#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
1792#define FDL_TP1_TIMER_SHIFT 12
1793#define FDL_TP1_TIMER_MASK (3 << 12)
1794#define FDL_TP2_TIMER_SHIFT 10
1795#define FDL_TP2_TIMER_MASK (3 << 10)
1796#define RAWCLK_FREQ_MASK 0x3ff
1797#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
1798#define CNP_RAWCLK_DIV(div) ((div) << 16)
1799#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
1800#define CNP_RAWCLK_DEN(den) ((den) << 26)
1801#define ICP_RAWCLK_NUM(num) ((num) << 11)
1802
1803#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
1804
1805#define PCH_SSC4_PARMS _MMIO(0xc6210)
1806#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
1807
1808#define PCH_DPLL_SEL _MMIO(0xc7000)
1809#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
1810#define TRANS_DPLLA_SEL(pipe) 0
1811#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
1812
1813/* transcoder */
1814#define _PCH_TRANS_HTOTAL_A 0xe0000
1815#define _PCH_TRANS_HTOTAL_B 0xe1000
1816#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
1817#define TRANS_HTOTAL_SHIFT 16
1818#define TRANS_HACTIVE_SHIFT 0
1819
1820#define _PCH_TRANS_HBLANK_A 0xe0004
1821#define _PCH_TRANS_HBLANK_B 0xe1004
1822#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
1823#define TRANS_HBLANK_END_SHIFT 16
1824#define TRANS_HBLANK_START_SHIFT 0
1825
1826#define _PCH_TRANS_HSYNC_A 0xe0008
1827#define _PCH_TRANS_HSYNC_B 0xe1008
1828#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
1829#define TRANS_HSYNC_END_SHIFT 16
1830#define TRANS_HSYNC_START_SHIFT 0
1831
1832#define _PCH_TRANS_VTOTAL_A 0xe000c
1833#define _PCH_TRANS_VTOTAL_B 0xe100c
1834#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
1835#define TRANS_VTOTAL_SHIFT 16
1836#define TRANS_VACTIVE_SHIFT 0
1837
1838#define _PCH_TRANS_VBLANK_A 0xe0010
1839#define _PCH_TRANS_VBLANK_B 0xe1010
1840#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
1841#define TRANS_VBLANK_END_SHIFT 16
1842#define TRANS_VBLANK_START_SHIFT 0
1843
1844#define _PCH_TRANS_VSYNC_A 0xe0014
1845#define _PCH_TRANS_VSYNC_B 0xe1014
1846#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
1847#define TRANS_VSYNC_END_SHIFT 16
1848#define TRANS_VSYNC_START_SHIFT 0
1849
1850#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
1851#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
1852#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
1853
1854#define _PCH_TRANSA_DATA_M1 0xe0030
1855#define _PCH_TRANSB_DATA_M1 0xe1030
1856#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
1857
1858#define _PCH_TRANSA_DATA_N1 0xe0034
1859#define _PCH_TRANSB_DATA_N1 0xe1034
1860#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
1861
1862#define _PCH_TRANSA_DATA_M2 0xe0038
1863#define _PCH_TRANSB_DATA_M2 0xe1038
1864#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
1865
1866#define _PCH_TRANSA_DATA_N2 0xe003c
1867#define _PCH_TRANSB_DATA_N2 0xe103c
1868#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
1869
1870#define _PCH_TRANSA_LINK_M1 0xe0040
1871#define _PCH_TRANSB_LINK_M1 0xe1040
1872#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
1873
1874#define _PCH_TRANSA_LINK_N1 0xe0044
1875#define _PCH_TRANSB_LINK_N1 0xe1044
1876#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
1877
1878#define _PCH_TRANSA_LINK_M2 0xe0048
1879#define _PCH_TRANSB_LINK_M2 0xe1048
1880#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
1881
1882#define _PCH_TRANSA_LINK_N2 0xe004c
1883#define _PCH_TRANSB_LINK_N2 0xe104c
1884#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
1885
1886/* Per-transcoder DIP controls (PCH) */
1887#define _VIDEO_DIP_CTL_A 0xe0200
1888#define _VIDEO_DIP_CTL_B 0xe1200
1889#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
1890
1891#define _VIDEO_DIP_DATA_A 0xe0208
1892#define _VIDEO_DIP_DATA_B 0xe1208
1893#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
1894
1895#define _VIDEO_DIP_GCP_A 0xe0210
1896#define _VIDEO_DIP_GCP_B 0xe1210
1897#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
1898#define GCP_COLOR_INDICATION (1 << 2)
1899#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
1900#define GCP_AV_MUTE (1 << 0)
1901
1902/* Per-transcoder DIP controls (VLV) */
1903#define _VLV_VIDEO_DIP_CTL_A 0x60200
1904#define _VLV_VIDEO_DIP_CTL_B 0x61170
1905#define _CHV_VIDEO_DIP_CTL_C 0x611f0
1906#define VLV_TVIDEO_DIP_CTL(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
1907 _VLV_VIDEO_DIP_CTL_A, \
1908 _VLV_VIDEO_DIP_CTL_B, \
1909 _CHV_VIDEO_DIP_CTL_C)
1910
1911#define _VLV_VIDEO_DIP_DATA_A 0x60208
1912#define _VLV_VIDEO_DIP_DATA_B 0x61174
1913#define _CHV_VIDEO_DIP_DATA_C 0x611f4
1914#define VLV_TVIDEO_DIP_DATA(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
1915 _VLV_VIDEO_DIP_DATA_A, \
1916 _VLV_VIDEO_DIP_DATA_B, \
1917 _CHV_VIDEO_DIP_DATA_C)
1918
1919#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
1920#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
1921#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8
1922#define VLV_TVIDEO_DIP_GCP(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
1923 _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
1924 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, \
1925 _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
1926
1927/* Haswell DIP controls */
1928#define _HSW_VIDEO_DIP_CTL_A 0x60200
1929#define _HSW_VIDEO_DIP_CTL_B 0x61200
1930#define HSW_TVIDEO_DIP_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A)
1931
1932#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
1933#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
1934#define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
1935
1936#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
1937#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
1938#define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
1939
1940#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
1941#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
1942#define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
1943
1944#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
1945#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
1946#define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
1947
1948#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
1949#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
1950#define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
1951
1952/*ADLP and later: */
1953#define _ADL_VIDEO_DIP_AS_DATA_A 0x60484
1954#define _ADL_VIDEO_DIP_AS_DATA_B 0x61484
1955#define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans,\
1956 _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4)
1957
1958#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
1959#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
1960#define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
1961
1962#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
1963#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
1964#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
1965#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
1966#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
1967#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
1968#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
1969#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
1970#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
1971#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
1972
1973#define _HSW_VIDEO_DIP_GCP_A 0x60210
1974#define _HSW_VIDEO_DIP_GCP_B 0x61210
1975#define HSW_TVIDEO_DIP_GCP(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A)
1976
1977#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
1978#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
1979#define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
1980
1981#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
1982#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
1983#define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
1984
1985#define _HSW_STEREO_3D_CTL_A 0x70020
1986#define _HSW_STEREO_3D_CTL_B 0x71020
1987#define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
1988#define S3D_ENABLE (1 << 31)
1989
1990#define _PCH_TRANSACONF 0xf0008
1991#define _PCH_TRANSBCONF 0xf1008
1992#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
1993#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
1994#define TRANS_ENABLE REG_BIT(31)
1995#define TRANS_STATE_ENABLE REG_BIT(30)
1996#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
1997#define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
1998#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
1999#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
2000#define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
2001#define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
2002#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
2003#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
2004#define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
2005#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
2006#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
2007
2008#define PCH_DP_B _MMIO(0xe4100)
2009#define PCH_DP_C _MMIO(0xe4200)
2010#define PCH_DP_D _MMIO(0xe4300)
2011
2012/* CPT */
2013#define _TRANS_DP_CTL_A 0xe0300
2014#define _TRANS_DP_CTL_B 0xe1300
2015#define _TRANS_DP_CTL_C 0xe2300
2016#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
2017#define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
2018#define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
2019#define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
2020#define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
2021#define TRANS_DP_AUDIO_ONLY REG_BIT(26)
2022#define TRANS_DP_ENH_FRAMING REG_BIT(18)
2023#define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
2024#define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
2025#define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
2026#define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
2027#define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
2028#define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
2029#define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
2030
2031#define _TRANS_DP2_CTL_A 0x600a0
2032#define _TRANS_DP2_CTL_B 0x610a0
2033#define _TRANS_DP2_CTL_C 0x620a0
2034#define _TRANS_DP2_CTL_D 0x630a0
2035#define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
2036#define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
2037#define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
2038#define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
2039
2040#define _TRANS_DP2_VFREQHIGH_A 0x600a4
2041#define _TRANS_DP2_VFREQHIGH_B 0x610a4
2042#define _TRANS_DP2_VFREQHIGH_C 0x620a4
2043#define _TRANS_DP2_VFREQHIGH_D 0x630a4
2044#define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
2045#define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
2046#define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
2047
2048#define _TRANS_DP2_VFREQLOW_A 0x600a8
2049#define _TRANS_DP2_VFREQLOW_B 0x610a8
2050#define _TRANS_DP2_VFREQLOW_C 0x620a8
2051#define _TRANS_DP2_VFREQLOW_D 0x630a8
2052#define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
2053
2054#define _DP_MIN_HBLANK_CTL_A 0x600ac
2055#define _DP_MIN_HBLANK_CTL_B 0x610ac
2056#define DP_MIN_HBLANK_CTL(trans) _MMIO_TRANS(trans, _DP_MIN_HBLANK_CTL_A, _DP_MIN_HBLANK_CTL_B)
2057
2058/* SNB eDP training params */
2059/* SNB A-stepping */
2060#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
2061#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
2062#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
2063#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
2064/* SNB B-stepping */
2065#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
2066#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
2067#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
2068#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
2069#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
2070#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
2071
2072/* IVB */
2073#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
2074#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
2075#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
2076#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
2077#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
2078#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
2079#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
2080
2081/* legacy values */
2082#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
2083#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
2084#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
2085#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
2086#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
2087
2088#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
2089
2090#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
2091#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
2092#define PIXEL_OVERLAP_CNT_SHIFT 30
2093
2094/*
2095 * HSW - ICL power wells
2096 *
2097 * Platforms have up to 3 power well control register sets, each set
2098 * controlling up to 16 power wells via a request/status HW flag tuple:
2099 * - main (HSW_PWR_WELL_CTL[1-4])
2100 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
2101 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
2102 * Each control register set consists of up to 4 registers used by different
2103 * sources that can request a power well to be enabled:
2104 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
2105 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
2106 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
2107 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
2108 */
2109#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
2110#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
2111#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
2112#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
2113#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
2114#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
2115
2116/* HSW/BDW power well */
2117#define HSW_PW_CTL_IDX_GLOBAL 15
2118
2119/* SKL/BXT/GLK power wells */
2120#define SKL_PW_CTL_IDX_PW_2 15
2121#define SKL_PW_CTL_IDX_PW_1 14
2122#define GLK_PW_CTL_IDX_AUX_C 10
2123#define GLK_PW_CTL_IDX_AUX_B 9
2124#define GLK_PW_CTL_IDX_AUX_A 8
2125#define SKL_PW_CTL_IDX_DDI_D 4
2126#define SKL_PW_CTL_IDX_DDI_C 3
2127#define SKL_PW_CTL_IDX_DDI_B 2
2128#define SKL_PW_CTL_IDX_DDI_A_E 1
2129#define GLK_PW_CTL_IDX_DDI_A 1
2130#define SKL_PW_CTL_IDX_MISC_IO 0
2131
2132/* ICL/TGL - power wells */
2133#define TGL_PW_CTL_IDX_PW_5 4
2134#define ICL_PW_CTL_IDX_PW_4 3
2135#define ICL_PW_CTL_IDX_PW_3 2
2136#define ICL_PW_CTL_IDX_PW_2 1
2137#define ICL_PW_CTL_IDX_PW_1 0
2138
2139/* XE_LPD - power wells */
2140#define XELPD_PW_CTL_IDX_PW_D 8
2141#define XELPD_PW_CTL_IDX_PW_C 7
2142#define XELPD_PW_CTL_IDX_PW_B 6
2143#define XELPD_PW_CTL_IDX_PW_A 5
2144
2145#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
2146#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
2147#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
2148#define TGL_PW_CTL_IDX_AUX_TBT6 14
2149#define TGL_PW_CTL_IDX_AUX_TBT5 13
2150#define TGL_PW_CTL_IDX_AUX_TBT4 12
2151#define ICL_PW_CTL_IDX_AUX_TBT4 11
2152#define TGL_PW_CTL_IDX_AUX_TBT3 11
2153#define ICL_PW_CTL_IDX_AUX_TBT3 10
2154#define TGL_PW_CTL_IDX_AUX_TBT2 10
2155#define ICL_PW_CTL_IDX_AUX_TBT2 9
2156#define TGL_PW_CTL_IDX_AUX_TBT1 9
2157#define ICL_PW_CTL_IDX_AUX_TBT1 8
2158#define TGL_PW_CTL_IDX_AUX_TC6 8
2159#define XELPD_PW_CTL_IDX_AUX_E 8
2160#define TGL_PW_CTL_IDX_AUX_TC5 7
2161#define XELPD_PW_CTL_IDX_AUX_D 7
2162#define TGL_PW_CTL_IDX_AUX_TC4 6
2163#define ICL_PW_CTL_IDX_AUX_F 5
2164#define TGL_PW_CTL_IDX_AUX_TC3 5
2165#define ICL_PW_CTL_IDX_AUX_E 4
2166#define TGL_PW_CTL_IDX_AUX_TC2 4
2167#define ICL_PW_CTL_IDX_AUX_D 3
2168#define TGL_PW_CTL_IDX_AUX_TC1 3
2169#define ICL_PW_CTL_IDX_AUX_C 2
2170#define ICL_PW_CTL_IDX_AUX_B 1
2171#define ICL_PW_CTL_IDX_AUX_A 0
2172
2173#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
2174#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
2175#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
2176#define XELPD_PW_CTL_IDX_DDI_E 8
2177#define TGL_PW_CTL_IDX_DDI_TC6 8
2178#define XELPD_PW_CTL_IDX_DDI_D 7
2179#define TGL_PW_CTL_IDX_DDI_TC5 7
2180#define TGL_PW_CTL_IDX_DDI_TC4 6
2181#define ICL_PW_CTL_IDX_DDI_F 5
2182#define TGL_PW_CTL_IDX_DDI_TC3 5
2183#define ICL_PW_CTL_IDX_DDI_E 4
2184#define TGL_PW_CTL_IDX_DDI_TC2 4
2185#define ICL_PW_CTL_IDX_DDI_D 3
2186#define TGL_PW_CTL_IDX_DDI_TC1 3
2187#define ICL_PW_CTL_IDX_DDI_C 2
2188#define ICL_PW_CTL_IDX_DDI_B 1
2189#define ICL_PW_CTL_IDX_DDI_A 0
2190
2191/* HSW - power well misc debug registers */
2192#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
2193#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
2194#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
2195#define HSW_PWR_WELL_FORCE_ON (1 << 19)
2196#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
2197
2198/* SKL Fuse Status */
2199enum skl_power_gate {
2200 SKL_PG0,
2201 SKL_PG1,
2202 SKL_PG2,
2203 ICL_PG3,
2204 ICL_PG4,
2205};
2206
2207#define SKL_FUSE_STATUS _MMIO(0x42000)
2208#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
2209#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
2210
2211/* Per-pipe DDI Function Control */
2212#define _TRANS_DDI_FUNC_CTL_A 0x60400
2213#define _TRANS_DDI_FUNC_CTL_B 0x61400
2214#define _TRANS_DDI_FUNC_CTL_C 0x62400
2215#define _TRANS_DDI_FUNC_CTL_D 0x63400
2216#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
2217#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
2218#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
2219#define TRANS_DDI_FUNC_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A)
2220
2221#define TRANS_DDI_FUNC_ENABLE (1 << 31)
2222/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
2223#define TRANS_DDI_PORT_SHIFT 28
2224#define TGL_TRANS_DDI_PORT_SHIFT 27
2225#define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
2226#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
2227#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
2228#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
2229#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
2230#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
2231#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
2232#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
2233#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
2234#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24)
2235#define TRANS_DDI_BPC_MASK (7 << 20)
2236#define TRANS_DDI_BPC_8 (0 << 20)
2237#define TRANS_DDI_BPC_10 (1 << 20)
2238#define TRANS_DDI_BPC_6 (2 << 20)
2239#define TRANS_DDI_BPC_12 (3 << 20)
2240#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
2241#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
2242#define TRANS_DDI_PVSYNC (1 << 17)
2243#define TRANS_DDI_PHSYNC (1 << 16)
2244#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
2245#define XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(15)
2246#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
2247#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
2248#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
2249#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
2250#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
2251#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
2252#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12)
2253#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
2254#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
2255 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
2256#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
2257#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
2258#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
2259#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
2260#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
2261#define TRANS_DDI_BFI_ENABLE (1 << 4)
2262#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
2263#define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
2264#define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
2265#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
2266#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
2267 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
2268 | TRANS_DDI_HDMI_SCRAMBLING)
2269
2270#define _TRANS_DDI_FUNC_CTL2_A 0x60404
2271#define _TRANS_DDI_FUNC_CTL2_B 0x61404
2272#define _TRANS_DDI_FUNC_CTL2_C 0x62404
2273#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
2274#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
2275#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
2276#define TRANS_DDI_FUNC_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A)
2277#define PORT_SYNC_MODE_ENABLE REG_BIT(4)
2278#define CMTG_SECONDARY_MODE REG_BIT(3)
2279#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
2280#define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
2281
2282#define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
2283#define DISABLE_DPT_CLK_GATING REG_BIT(1)
2284
2285/* DisplayPort Transport Control */
2286#define _DP_TP_CTL_A 0x64040
2287#define _DP_TP_CTL_B 0x64140
2288#define _TGL_DP_TP_CTL_A 0x60540
2289#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
2290#define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A)
2291#define DP_TP_CTL_ENABLE REG_BIT(31)
2292#define DP_TP_CTL_FEC_ENABLE REG_BIT(30)
2293#define DP_TP_CTL_MODE_MASK REG_BIT(27)
2294#define DP_TP_CTL_MODE_SST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 0)
2295#define DP_TP_CTL_MODE_MST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 1)
2296#define DP_TP_CTL_FORCE_ACT REG_BIT(25)
2297#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK REG_GENMASK(20, 19)
2298#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 0)
2299#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 1)
2300#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 2)
2301#define DP_TP_CTL_ENHANCED_FRAME_ENABLE REG_BIT(18)
2302#define DP_TP_CTL_FDI_AUTOTRAIN REG_BIT(15)
2303#define DP_TP_CTL_LINK_TRAIN_MASK REG_GENMASK(10, 8)
2304#define DP_TP_CTL_LINK_TRAIN_PAT1 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 0)
2305#define DP_TP_CTL_LINK_TRAIN_PAT2 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 1)
2306#define DP_TP_CTL_LINK_TRAIN_PAT3 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 4)
2307#define DP_TP_CTL_LINK_TRAIN_PAT4 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 5)
2308#define DP_TP_CTL_LINK_TRAIN_IDLE REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 2)
2309#define DP_TP_CTL_LINK_TRAIN_NORMAL REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 3)
2310#define DP_TP_CTL_SCRAMBLE_DISABLE REG_BIT(7)
2311
2312/* DisplayPort Transport Status */
2313#define _DP_TP_STATUS_A 0x64044
2314#define _DP_TP_STATUS_B 0x64144
2315#define _TGL_DP_TP_STATUS_A 0x60544
2316#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
2317#define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A)
2318#define DP_TP_STATUS_FEC_ENABLE_LIVE REG_BIT(28)
2319#define DP_TP_STATUS_IDLE_DONE REG_BIT(25)
2320#define DP_TP_STATUS_ACT_SENT REG_BIT(24)
2321#define DP_TP_STATUS_MODE_STATUS_MST REG_BIT(23)
2322#define DP_TP_STATUS_STREAMS_ENABLED_MASK REG_GENMASK(18, 16) /* 17:16 on hsw but bit 18 mbz */
2323#define DP_TP_STATUS_AUTOTRAIN_DONE REG_BIT(12)
2324#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2_MASK REG_GENMASK(9, 8)
2325#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1_MASK REG_GENMASK(5, 4)
2326#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0_MASK REG_GENMASK(1, 0)
2327
2328/* DDI Buffer Control */
2329#define _DDI_BUF_CTL_A 0x64000
2330#define _DDI_BUF_CTL_B 0x64100
2331/* Known as DDI_CTL_DE in MTL+ */
2332#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
2333#define DDI_BUF_CTL_ENABLE REG_BIT(31)
2334#define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29)
2335#define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
2336#define DDI_BUF_EMP_MASK REG_GENMASK(27, 24)
2337#define DDI_BUF_TRANS_SELECT(n) REG_FIELD_PREP(DDI_BUF_EMP_MASK, (n))
2338#define DDI_BUF_PHY_LINK_RATE_MASK REG_GENMASK(23, 20)
2339#define DDI_BUF_PHY_LINK_RATE(r) REG_FIELD_PREP(DDI_BUF_PHY_LINK_RATE_MASK, (r))
2340#define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18)
2341#define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0)
2342#define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1)
2343#define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2)
2344#define DDI_BUF_PORT_REVERSAL REG_BIT(16)
2345#define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8)
2346#define DDI_BUF_LANE_STAGGER_DELAY(symbols) REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \
2347 (symbols))
2348#define DDI_BUF_IS_IDLE REG_BIT(7)
2349#define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
2350#define DDI_A_4_LANES REG_BIT(4)
2351#define DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
2352#define DDI_PORT_WIDTH(width) REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \
2353 ((width) == 3 ? 4 : (width) - 1))
2354#define DDI_PORT_WIDTH_SHIFT 1
2355#define DDI_INIT_DISPLAY_DETECTED REG_BIT(0)
2356
2357/* DDI Buffer Translations */
2358#define _DDI_BUF_TRANS_A 0x64E00
2359#define _DDI_BUF_TRANS_B 0x64E60
2360#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
2361#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
2362#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
2363
2364/* DDI DP Compliance Control */
2365#define _DDI_DP_COMP_CTL_A 0x605F0
2366#define _DDI_DP_COMP_CTL_B 0x615F0
2367#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
2368#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
2369#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
2370#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
2371#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
2372#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
2373#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
2374#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
2375#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
2376
2377/* DDI DP Compliance Pattern */
2378#define _DDI_DP_COMP_PAT_A 0x605F4
2379#define _DDI_DP_COMP_PAT_B 0x615F4
2380#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
2381
2382/* LPT PIXCLK_GATE */
2383#define PIXCLK_GATE _MMIO(0xC6020)
2384#define PIXCLK_GATE_UNGATE (1 << 0)
2385#define PIXCLK_GATE_GATE (0 << 0)
2386
2387/* SPLL */
2388#define SPLL_CTL _MMIO(0x46020)
2389#define SPLL_PLL_ENABLE (1 << 31)
2390#define SPLL_REF_BCLK (0 << 28)
2391#define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
2392#define SPLL_REF_NON_SSC_HSW (2 << 28)
2393#define SPLL_REF_PCH_SSC_BDW (2 << 28)
2394#define SPLL_REF_LCPLL (3 << 28)
2395#define SPLL_REF_MASK (3 << 28)
2396#define SPLL_FREQ_810MHz (0 << 26)
2397#define SPLL_FREQ_1350MHz (1 << 26)
2398#define SPLL_FREQ_2700MHz (2 << 26)
2399#define SPLL_FREQ_MASK (3 << 26)
2400
2401/* WRPLL */
2402#define _WRPLL_CTL1 0x46040
2403#define _WRPLL_CTL2 0x46060
2404#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
2405#define WRPLL_PLL_ENABLE (1 << 31)
2406#define WRPLL_REF_BCLK (0 << 28)
2407#define WRPLL_REF_PCH_SSC (1 << 28)
2408#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
2409#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
2410#define WRPLL_REF_LCPLL (3 << 28)
2411#define WRPLL_REF_MASK (3 << 28)
2412/* WRPLL divider programming */
2413#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
2414#define WRPLL_DIVIDER_REF_MASK (0xff)
2415#define WRPLL_DIVIDER_POST(x) ((x) << 8)
2416#define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
2417#define WRPLL_DIVIDER_POST_SHIFT 8
2418#define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
2419#define WRPLL_DIVIDER_FB_SHIFT 16
2420#define WRPLL_DIVIDER_FB_MASK (0xff << 16)
2421
2422/* Port clock selection */
2423#define _PORT_CLK_SEL_A 0x46100
2424#define _PORT_CLK_SEL_B 0x46104
2425#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
2426#define PORT_CLK_SEL_MASK REG_GENMASK(31, 29)
2427#define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
2428#define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1)
2429#define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2)
2430#define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3)
2431#define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll))
2432#define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4)
2433#define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5)
2434#define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)
2435
2436/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
2437#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
2438#define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
2439#define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
2440#define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
2441#define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
2442#define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
2443#define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
2444#define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
2445
2446/* Transcoder clock selection */
2447#define _TRANS_CLK_SEL_A 0x46140
2448#define _TRANS_CLK_SEL_B 0x46144
2449#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
2450/* For each transcoder, we need to select the corresponding port clock */
2451#define TRANS_CLK_SEL_DISABLED (0x0 << 29)
2452#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
2453#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
2454#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
2455
2456#define CDCLK_FREQ _MMIO(0x46200)
2457
2458#define _TRANSA_MSA_MISC 0x60410
2459#define _TRANSB_MSA_MISC 0x61410
2460#define _TRANSC_MSA_MISC 0x62410
2461#define _TRANS_EDP_MSA_MISC 0x6f410
2462#define TRANS_MSA_MISC(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC)
2463/* See DP_MSA_MISC_* for the bit definitions */
2464
2465#define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
2466#define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
2467#define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
2468#define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
2469#define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY)
2470#define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
2471#define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
2472
2473/* LCPLL Control */
2474#define LCPLL_CTL _MMIO(0x130040)
2475#define LCPLL_PLL_DISABLE (1 << 31)
2476#define LCPLL_PLL_LOCK (1 << 30)
2477#define LCPLL_REF_NON_SSC (0 << 28)
2478#define LCPLL_REF_BCLK (2 << 28)
2479#define LCPLL_REF_PCH_SSC (3 << 28)
2480#define LCPLL_REF_MASK (3 << 28)
2481#define LCPLL_CLK_FREQ_MASK (3 << 26)
2482#define LCPLL_CLK_FREQ_450 (0 << 26)
2483#define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
2484#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
2485#define LCPLL_CLK_FREQ_675_BDW (3 << 26)
2486#define LCPLL_CD_CLOCK_DISABLE (1 << 25)
2487#define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
2488#define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
2489#define LCPLL_POWER_DOWN_ALLOW (1 << 22)
2490#define LCPLL_CD_SOURCE_FCLK (1 << 21)
2491#define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
2492
2493/*
2494 * SKL Clocks
2495 */
2496/* CDCLK_CTL */
2497#define CDCLK_CTL _MMIO(0x46000)
2498#define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26)
2499#define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
2500#define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
2501#define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
2502#define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
2503#define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25)
2504#define MDCLK_SOURCE_SEL_CD2XCLK REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0)
2505#define MDCLK_SOURCE_SEL_CDCLK_PLL REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1)
2506#define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
2507#define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
2508#define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
2509#define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2)
2510#define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3)
2511#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
2512#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
2513#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
2514#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
2515#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
2516#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
2517#define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE
2518#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
2519#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
2520
2521/* CDCLK_SQUASH_CTL */
2522#define CDCLK_SQUASH_CTL _MMIO(0x46008)
2523#define CDCLK_SQUASH_ENABLE REG_BIT(31)
2524#define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24)
2525#define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x))
2526#define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
2527#define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x))
2528
2529/* LCPLL_CTL */
2530#define LCPLL1_CTL _MMIO(0x46010)
2531#define LCPLL2_CTL _MMIO(0x46014)
2532#define LCPLL_PLL_ENABLE (1 << 31)
2533
2534/* DPLL control1 */
2535#define DPLL_CTRL1 _MMIO(0x6C058)
2536#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
2537#define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
2538#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
2539#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
2540#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
2541#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
2542#define DPLL_CTRL1_LINK_RATE_2700 0
2543#define DPLL_CTRL1_LINK_RATE_1350 1
2544#define DPLL_CTRL1_LINK_RATE_810 2
2545#define DPLL_CTRL1_LINK_RATE_1620 3
2546#define DPLL_CTRL1_LINK_RATE_1080 4
2547#define DPLL_CTRL1_LINK_RATE_2160 5
2548
2549/* DPLL control2 */
2550#define DPLL_CTRL2 _MMIO(0x6C05C)
2551#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
2552#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
2553#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
2554#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
2555#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
2556
2557/* DPLL Status */
2558#define DPLL_STATUS _MMIO(0x6C060)
2559#define DPLL_LOCK(id) (1 << ((id) * 8))
2560
2561/* DPLL cfg */
2562#define _DPLL1_CFGCR1 0x6C040
2563#define _DPLL2_CFGCR1 0x6C048
2564#define _DPLL3_CFGCR1 0x6C050
2565#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
2566#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
2567#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
2568#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
2569#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
2570
2571#define _DPLL1_CFGCR2 0x6C044
2572#define _DPLL2_CFGCR2 0x6C04C
2573#define _DPLL3_CFGCR2 0x6C054
2574#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
2575#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
2576#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
2577#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
2578#define DPLL_CFGCR2_KDIV_MASK (3 << 5)
2579#define DPLL_CFGCR2_KDIV(x) ((x) << 5)
2580#define DPLL_CFGCR2_KDIV_5 (0 << 5)
2581#define DPLL_CFGCR2_KDIV_2 (1 << 5)
2582#define DPLL_CFGCR2_KDIV_3 (2 << 5)
2583#define DPLL_CFGCR2_KDIV_1 (3 << 5)
2584#define DPLL_CFGCR2_PDIV_MASK (7 << 2)
2585#define DPLL_CFGCR2_PDIV(x) ((x) << 2)
2586#define DPLL_CFGCR2_PDIV_1 (0 << 2)
2587#define DPLL_CFGCR2_PDIV_2 (1 << 2)
2588#define DPLL_CFGCR2_PDIV_3 (2 << 2)
2589#define DPLL_CFGCR2_PDIV_7 (4 << 2)
2590#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
2591#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
2592
2593/* ICL Clocks */
2594#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
2595#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
2596#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
2597#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
2598 (tc_port) + 12 : \
2599 (tc_port) - TC_PORT_4 + 21))
2600#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
2601#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
2602#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
2603#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
2604#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
2605 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
2606#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
2607 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
2608
2609/*
2610 * DG1 Clocks
2611 * First registers controls the first A and B, while the second register
2612 * controls the phy C and D. The bits on these registers are the
2613 * same, but refer to different phys
2614 */
2615#define _DG1_DPCLKA_CFGCR0 0x164280
2616#define _DG1_DPCLKA1_CFGCR0 0x16C280
2617#define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
2618#define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
2619#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
2620 _DG1_DPCLKA_CFGCR0, \
2621 _DG1_DPCLKA1_CFGCR0)
2622#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
2623#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2)
2624#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
2625#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
2626
2627/* ADLS Clocks */
2628#define _ADLS_DPCLKA_CFGCR0 0x164280
2629#define _ADLS_DPCLKA_CFGCR1 0x1642BC
2630#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \
2631 _ADLS_DPCLKA_CFGCR0, \
2632 _ADLS_DPCLKA_CFGCR1)
2633#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2)
2634/* ADLS DPCLKA_CFGCR0 DDI mask */
2635#define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4)
2636#define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2)
2637#define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
2638/* ADLS DPCLKA_CFGCR1 DDI mask */
2639#define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2)
2640#define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
2641#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
2642 ADLS_DPCLKA_DDIA_SEL_MASK, \
2643 ADLS_DPCLKA_DDIB_SEL_MASK, \
2644 ADLS_DPCLKA_DDII_SEL_MASK, \
2645 ADLS_DPCLKA_DDIJ_SEL_MASK, \
2646 ADLS_DPCLKA_DDIK_SEL_MASK)
2647
2648/* ICL PLL */
2649#define _DPLL0_ENABLE 0x46010
2650#define _DPLL1_ENABLE 0x46014
2651#define _ADLS_DPLL2_ENABLE 0x46018
2652#define _ADLS_DPLL3_ENABLE 0x46030
2653#define PLL_ENABLE REG_BIT(31)
2654#define PLL_LOCK REG_BIT(30)
2655#define PLL_POWER_ENABLE REG_BIT(27)
2656#define PLL_POWER_STATE REG_BIT(26)
2657#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
2658 _DPLL0_ENABLE, _DPLL1_ENABLE, \
2659 _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
2660
2661#define _DG2_PLL3_ENABLE 0x4601C
2662
2663#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
2664 _DPLL0_ENABLE, _DPLL1_ENABLE, \
2665 _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE))
2666
2667#define TBT_PLL_ENABLE _MMIO(0x46020)
2668
2669#define _MG_PLL1_ENABLE 0x46030
2670#define _MG_PLL2_ENABLE 0x46034
2671#define _MG_PLL3_ENABLE 0x46038
2672#define _MG_PLL4_ENABLE 0x4603C
2673/* Bits are the same as _DPLL0_ENABLE */
2674#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
2675 _MG_PLL2_ENABLE)
2676
2677/* DG1 PLL */
2678#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
2679 _DPLL0_ENABLE, _DPLL1_ENABLE, \
2680 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE))
2681
2682/* ADL-P Type C PLL */
2683#define PORTTC1_PLL_ENABLE 0x46038
2684#define PORTTC2_PLL_ENABLE 0x46040
2685#define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \
2686 PORTTC1_PLL_ENABLE, \
2687 PORTTC2_PLL_ENABLE)
2688
2689#define _ICL_DPLL0_CFGCR0 0x164000
2690#define _ICL_DPLL1_CFGCR0 0x164080
2691#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
2692 _ICL_DPLL1_CFGCR0)
2693#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
2694#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
2695#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
2696#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
2697#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
2698#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
2699#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
2700#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
2701#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
2702#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
2703#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
2704#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
2705#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
2706#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
2707#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
2708#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
2709
2710#define _ICL_DPLL0_CFGCR1 0x164004
2711#define _ICL_DPLL1_CFGCR1 0x164084
2712#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
2713 _ICL_DPLL1_CFGCR1)
2714#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
2715#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
2716#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
2717#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
2718#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
2719#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
2720#define DPLL_CFGCR1_KDIV_SHIFT (6)
2721#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
2722#define DPLL_CFGCR1_KDIV_1 (1 << 6)
2723#define DPLL_CFGCR1_KDIV_2 (2 << 6)
2724#define DPLL_CFGCR1_KDIV_3 (4 << 6)
2725#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
2726#define DPLL_CFGCR1_PDIV_SHIFT (2)
2727#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
2728#define DPLL_CFGCR1_PDIV_2 (1 << 2)
2729#define DPLL_CFGCR1_PDIV_3 (2 << 2)
2730#define DPLL_CFGCR1_PDIV_5 (4 << 2)
2731#define DPLL_CFGCR1_PDIV_7 (8 << 2)
2732#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
2733#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
2734#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
2735
2736#define _TGL_DPLL0_CFGCR0 0x164284
2737#define _TGL_DPLL1_CFGCR0 0x16428C
2738#define _TGL_TBTPLL_CFGCR0 0x16429C
2739#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
2740 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
2741 _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0))
2742#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
2743 _TGL_DPLL1_CFGCR0)
2744
2745#define _TGL_DPLL0_DIV0 0x164B00
2746#define _TGL_DPLL1_DIV0 0x164C00
2747#define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)
2748#define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
2749#define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))
2750
2751#define _TGL_DPLL0_CFGCR1 0x164288
2752#define _TGL_DPLL1_CFGCR1 0x164290
2753#define _TGL_TBTPLL_CFGCR1 0x1642A0
2754#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
2755 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
2756 _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1))
2757#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
2758 _TGL_DPLL1_CFGCR1)
2759
2760#define _DG1_DPLL2_CFGCR0 0x16C284
2761#define _DG1_DPLL3_CFGCR0 0x16C28C
2762#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
2763 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
2764 _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0))
2765
2766#define _DG1_DPLL2_CFGCR1 0x16C288
2767#define _DG1_DPLL3_CFGCR1 0x16C290
2768#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
2769 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
2770 _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1))
2771
2772/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
2773#define _ADLS_DPLL4_CFGCR0 0x164294
2774#define _ADLS_DPLL3_CFGCR0 0x1642C0
2775#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
2776 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
2777 _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0))
2778
2779#define _ADLS_DPLL4_CFGCR1 0x164298
2780#define _ADLS_DPLL3_CFGCR1 0x1642C4
2781#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
2782 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
2783 _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1))
2784
2785/* BXT display engine PLL */
2786#define BXT_DE_PLL_CTL _MMIO(0x6d000)
2787#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
2788#define BXT_DE_PLL_RATIO_MASK 0xff
2789
2790#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
2791#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
2792#define BXT_DE_PLL_LOCK (1 << 30)
2793#define BXT_DE_PLL_FREQ_REQ (1 << 23)
2794#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
2795#define ICL_CDCLK_PLL_RATIO(x) (x)
2796#define ICL_CDCLK_PLL_RATIO_MASK 0xff
2797
2798/* GEN9 DC */
2799#define DC_STATE_EN _MMIO(0x45504)
2800#define DC_STATE_DISABLE 0
2801#define DC_STATE_EN_DC3CO REG_BIT(30)
2802#define DC_STATE_DC3CO_STATUS REG_BIT(29)
2803#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
2804#define HOLD_PHY_PG1_LATCH REG_BIT(20)
2805#define DC_STATE_EN_UPTO_DC5 (1 << 0)
2806#define DC_STATE_EN_DC9 (1 << 3)
2807#define DC_STATE_EN_UPTO_DC6 (2 << 0)
2808#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
2809
2810#define DC_STATE_DEBUG _MMIO(0x45520)
2811#define DC_STATE_DEBUG_MASK_CORES (1 << 0)
2812#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
2813
2814#define D_COMP_BDW _MMIO(0x138144)
2815
2816/* Pipe WM_LINETIME - watermark line time */
2817#define _WM_LINETIME_A 0x45270
2818#define _WM_LINETIME_B 0x45274
2819#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
2820#define HSW_LINETIME_MASK REG_GENMASK(8, 0)
2821#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
2822#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
2823#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
2824
2825/* SFUSE_STRAP */
2826#define SFUSE_STRAP _MMIO(0xc2014)
2827#define SFUSE_STRAP_FUSE_LOCK (1 << 13)
2828#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
2829#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
2830#define SFUSE_STRAP_CRT_DISABLED (1 << 6)
2831#define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
2832#define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
2833#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
2834#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
2835
2836/* Gen4+ Timestamp and Pipe Frame time stamp registers */
2837#define GEN4_TIMESTAMP _MMIO(0x2358)
2838#define ILK_TIMESTAMP_HI _MMIO(0x70070)
2839#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
2840
2841/* g4x+, except vlv/chv! */
2842#define _PIPE_FRMTMSTMP_A 0x70048
2843#define _PIPE_FRMTMSTMP_B 0x71048
2844#define PIPE_FRMTMSTMP(pipe) \
2845 _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B)
2846
2847/* g4x+, except vlv/chv! */
2848#define _PIPE_FLIPTMSTMP_A 0x7004C
2849#define _PIPE_FLIPTMSTMP_B 0x7104C
2850#define PIPE_FLIPTMSTMP(pipe) \
2851 _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B)
2852
2853/* tgl+ */
2854#define _PIPE_FLIPDONETMSTMP_A 0x70054
2855#define _PIPE_FLIPDONETMSTMP_B 0x71054
2856#define PIPE_FLIPDONETIMSTMP(pipe) \
2857 _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B)
2858
2859#define _VLV_PIPE_MSA_MISC_A 0x70048
2860#define VLV_PIPE_MSA_MISC(__display, pipe) \
2861 _MMIO_PIPE2(__display, pipe, _VLV_PIPE_MSA_MISC_A)
2862#define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
2863#define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
2864
2865#define _ICL_PHY_MISC_A 0x64C00
2866#define _ICL_PHY_MISC_B 0x64C04
2867#define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
2868#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
2869#define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
2870 ICL_PHY_MISC(port))
2871#define ICL_PHY_MISC_MUX_DDID (1 << 28)
2872#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
2873#define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
2874
2875#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
2876#define MODULAR_FIA_MASK (1 << 4)
2877#define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
2878#define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
2879#define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
2880#define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
2881#define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
2882
2883#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
2884#define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
2885
2886#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
2887#define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
2888
2889#define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
2890#define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
2891#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
2892#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
2893/* See enum intel_tc_pin_assignment for the pin assignment field values. */
2894
2895#define _TCSS_DDI_STATUS_1 0x161500
2896#define _TCSS_DDI_STATUS_2 0x161504
2897#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
2898 _TCSS_DDI_STATUS_1, \
2899 _TCSS_DDI_STATUS_2))
2900#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
2901/* See enum intel_tc_pin_assignment for the pin assignment field values. */
2902#define TCSS_DDI_STATUS_READY REG_BIT(2)
2903#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
2904#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
2905
2906#define CLKREQ_POLICY _MMIO(0x101038)
2907#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
2908
2909#define CLKGATE_DIS_MISC _MMIO(0x46534)
2910#define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
2911
2912#define _MTL_CLKGATE_DIS_TRANS_A 0x604E8
2913#define _MTL_CLKGATE_DIS_TRANS_B 0x614E8
2914#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
2915#define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7)
2916
2917#define _MTL_PIPE_CLKGATE_DIS2_A 0x60114
2918#define _MTL_PIPE_CLKGATE_DIS2_B 0x61114
2919#define MTL_PIPE_CLKGATE_DIS2(pipe) _MMIO_PIPE(pipe, _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B)
2920#define MTL_DPFC_GATING_DIS REG_BIT(6)
2921
2922#define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710
2923#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8)
2924#define MTL_TRCD_MASK REG_GENMASK(31, 24)
2925#define MTL_TRP_MASK REG_GENMASK(23, 16)
2926#define MTL_DCLK_MASK REG_GENMASK(15, 0)
2927
2928#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4)
2929#define MTL_TRAS_MASK REG_GENMASK(16, 8)
2930#define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
2931
2932
2933
2934#endif /* __INTEL_DISPLAY_REGS_H__ */
2935

source code of linux/drivers/gpu/drm/i915/display/intel_display_regs.h