| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2018 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_TPC0_QM_MASKS_H_ |
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| 14 | #define ASIC_REG_TPC0_QM_MASKS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * TPC0_QM (Prototype: QMAN) |
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| 19 | ***************************************** |
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| 20 | */ |
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| 21 | |
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| 22 | /* TPC0_QM_GLBL_CFG0 */ |
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| 23 | #define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 |
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| 24 | #define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0x1 |
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| 25 | #define TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT 1 |
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| 26 | #define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x2 |
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| 27 | #define TPC0_QM_GLBL_CFG0_CP_EN_SHIFT 2 |
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| 28 | #define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x4 |
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| 29 | #define TPC0_QM_GLBL_CFG0_DMA_EN_SHIFT 3 |
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| 30 | #define TPC0_QM_GLBL_CFG0_DMA_EN_MASK 0x8 |
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| 31 | |
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| 32 | /* TPC0_QM_GLBL_CFG1 */ |
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| 33 | #define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 |
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| 34 | #define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0x1 |
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| 35 | #define TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT 1 |
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| 36 | #define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x2 |
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| 37 | #define TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT 2 |
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| 38 | #define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x4 |
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| 39 | #define TPC0_QM_GLBL_CFG1_DMA_STOP_SHIFT 3 |
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| 40 | #define TPC0_QM_GLBL_CFG1_DMA_STOP_MASK 0x8 |
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| 41 | #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 8 |
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| 42 | #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0x100 |
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| 43 | #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 9 |
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| 44 | #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x200 |
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| 45 | #define TPC0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 10 |
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| 46 | #define TPC0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x400 |
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| 47 | #define TPC0_QM_GLBL_CFG1_DMA_FLUSH_SHIFT 11 |
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| 48 | #define TPC0_QM_GLBL_CFG1_DMA_FLUSH_MASK 0x800 |
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| 49 | |
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| 50 | /* TPC0_QM_GLBL_PROT */ |
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| 51 | #define TPC0_QM_GLBL_PROT_PQF_PROT_SHIFT 0 |
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| 52 | #define TPC0_QM_GLBL_PROT_PQF_PROT_MASK 0x1 |
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| 53 | #define TPC0_QM_GLBL_PROT_CQF_PROT_SHIFT 1 |
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| 54 | #define TPC0_QM_GLBL_PROT_CQF_PROT_MASK 0x2 |
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| 55 | #define TPC0_QM_GLBL_PROT_CP_PROT_SHIFT 2 |
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| 56 | #define TPC0_QM_GLBL_PROT_CP_PROT_MASK 0x4 |
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| 57 | #define TPC0_QM_GLBL_PROT_DMA_PROT_SHIFT 3 |
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| 58 | #define TPC0_QM_GLBL_PROT_DMA_PROT_MASK 0x8 |
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| 59 | #define TPC0_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT 4 |
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| 60 | #define TPC0_QM_GLBL_PROT_PQF_ERR_PROT_MASK 0x10 |
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| 61 | #define TPC0_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT 5 |
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| 62 | #define TPC0_QM_GLBL_PROT_CQF_ERR_PROT_MASK 0x20 |
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| 63 | #define TPC0_QM_GLBL_PROT_CP_ERR_PROT_SHIFT 6 |
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| 64 | #define TPC0_QM_GLBL_PROT_CP_ERR_PROT_MASK 0x40 |
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| 65 | #define TPC0_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT 7 |
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| 66 | #define TPC0_QM_GLBL_PROT_DMA_ERR_PROT_MASK 0x80 |
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| 67 | |
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| 68 | /* TPC0_QM_GLBL_ERR_CFG */ |
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| 69 | #define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT 0 |
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| 70 | #define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK 0x1 |
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| 71 | #define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 1 |
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| 72 | #define TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0x2 |
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| 73 | #define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 2 |
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| 74 | #define TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0x4 |
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| 75 | #define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT 3 |
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| 76 | #define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK 0x8 |
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| 77 | #define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 |
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| 78 | #define TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x10 |
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| 79 | #define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 5 |
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| 80 | #define TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x20 |
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| 81 | #define TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT 6 |
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| 82 | #define TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK 0x40 |
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| 83 | #define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 7 |
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| 84 | #define TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x80 |
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| 85 | #define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 8 |
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| 86 | #define TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x100 |
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| 87 | #define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT 9 |
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| 88 | #define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK 0x200 |
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| 89 | #define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT 10 |
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| 90 | #define TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK 0x400 |
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| 91 | #define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT 11 |
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| 92 | #define TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK 0x800 |
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| 93 | |
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| 94 | /* TPC0_QM_GLBL_ERR_ADDR_LO */ |
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| 95 | #define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 |
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| 96 | #define TPC0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF |
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| 97 | |
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| 98 | /* TPC0_QM_GLBL_ERR_ADDR_HI */ |
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| 99 | #define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 |
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| 100 | #define TPC0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF |
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| 101 | |
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| 102 | /* TPC0_QM_GLBL_ERR_WDATA */ |
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| 103 | #define TPC0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 |
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| 104 | #define TPC0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF |
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| 105 | |
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| 106 | /* TPC0_QM_GLBL_SECURE_PROPS */ |
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| 107 | #define TPC0_QM_GLBL_SECURE_PROPS_ASID_SHIFT 0 |
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| 108 | #define TPC0_QM_GLBL_SECURE_PROPS_ASID_MASK 0x3FF |
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| 109 | #define TPC0_QM_GLBL_SECURE_PROPS_MMBP_SHIFT 10 |
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| 110 | #define TPC0_QM_GLBL_SECURE_PROPS_MMBP_MASK 0x400 |
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| 111 | |
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| 112 | /* TPC0_QM_GLBL_NON_SECURE_PROPS */ |
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| 113 | #define TPC0_QM_GLBL_NON_SECURE_PROPS_ASID_SHIFT 0 |
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| 114 | #define TPC0_QM_GLBL_NON_SECURE_PROPS_ASID_MASK 0x3FF |
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| 115 | #define TPC0_QM_GLBL_NON_SECURE_PROPS_MMBP_SHIFT 10 |
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| 116 | #define TPC0_QM_GLBL_NON_SECURE_PROPS_MMBP_MASK 0x400 |
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| 117 | |
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| 118 | /* TPC0_QM_GLBL_STS0 */ |
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| 119 | #define TPC0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 |
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| 120 | #define TPC0_QM_GLBL_STS0_PQF_IDLE_MASK 0x1 |
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| 121 | #define TPC0_QM_GLBL_STS0_CQF_IDLE_SHIFT 1 |
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| 122 | #define TPC0_QM_GLBL_STS0_CQF_IDLE_MASK 0x2 |
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| 123 | #define TPC0_QM_GLBL_STS0_CP_IDLE_SHIFT 2 |
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| 124 | #define TPC0_QM_GLBL_STS0_CP_IDLE_MASK 0x4 |
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| 125 | #define TPC0_QM_GLBL_STS0_DMA_IDLE_SHIFT 3 |
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| 126 | #define TPC0_QM_GLBL_STS0_DMA_IDLE_MASK 0x8 |
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| 127 | #define TPC0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 4 |
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| 128 | #define TPC0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0x10 |
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| 129 | #define TPC0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 5 |
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| 130 | #define TPC0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x20 |
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| 131 | #define TPC0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 6 |
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| 132 | #define TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x40 |
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| 133 | #define TPC0_QM_GLBL_STS0_DMA_IS_STOP_SHIFT 7 |
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| 134 | #define TPC0_QM_GLBL_STS0_DMA_IS_STOP_MASK 0x80 |
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| 135 | |
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| 136 | /* TPC0_QM_GLBL_STS1 */ |
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| 137 | #define TPC0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT 0 |
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| 138 | #define TPC0_QM_GLBL_STS1_PQF_RD_ERR_MASK 0x1 |
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| 139 | #define TPC0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT 1 |
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| 140 | #define TPC0_QM_GLBL_STS1_CQF_RD_ERR_MASK 0x2 |
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| 141 | #define TPC0_QM_GLBL_STS1_CP_RD_ERR_SHIFT 2 |
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| 142 | #define TPC0_QM_GLBL_STS1_CP_RD_ERR_MASK 0x4 |
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| 143 | #define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT 3 |
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| 144 | #define TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK 0x8 |
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| 145 | #define TPC0_QM_GLBL_STS1_CP_STOP_OP_SHIFT 4 |
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| 146 | #define TPC0_QM_GLBL_STS1_CP_STOP_OP_MASK 0x10 |
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| 147 | #define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT 5 |
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| 148 | #define TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK 0x20 |
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| 149 | #define TPC0_QM_GLBL_STS1_DMA_RD_ERR_SHIFT 8 |
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| 150 | #define TPC0_QM_GLBL_STS1_DMA_RD_ERR_MASK 0x100 |
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| 151 | #define TPC0_QM_GLBL_STS1_DMA_WR_ERR_SHIFT 9 |
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| 152 | #define TPC0_QM_GLBL_STS1_DMA_WR_ERR_MASK 0x200 |
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| 153 | #define TPC0_QM_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT 10 |
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| 154 | #define TPC0_QM_GLBL_STS1_DMA_RD_MSG_ERR_MASK 0x400 |
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| 155 | #define TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT 11 |
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| 156 | #define TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_MASK 0x800 |
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| 157 | |
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| 158 | /* TPC0_QM_PQ_BASE_LO */ |
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| 159 | #define TPC0_QM_PQ_BASE_LO_VAL_SHIFT 0 |
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| 160 | #define TPC0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF |
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| 161 | |
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| 162 | /* TPC0_QM_PQ_BASE_HI */ |
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| 163 | #define TPC0_QM_PQ_BASE_HI_VAL_SHIFT 0 |
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| 164 | #define TPC0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF |
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| 165 | |
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| 166 | /* TPC0_QM_PQ_SIZE */ |
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| 167 | #define TPC0_QM_PQ_SIZE_VAL_SHIFT 0 |
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| 168 | #define TPC0_QM_PQ_SIZE_VAL_MASK 0xFFFFFFFF |
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| 169 | |
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| 170 | /* TPC0_QM_PQ_PI */ |
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| 171 | #define TPC0_QM_PQ_PI_VAL_SHIFT 0 |
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| 172 | #define TPC0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF |
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| 173 | |
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| 174 | /* TPC0_QM_PQ_CI */ |
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| 175 | #define TPC0_QM_PQ_CI_VAL_SHIFT 0 |
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| 176 | #define TPC0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF |
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| 177 | |
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| 178 | /* TPC0_QM_PQ_CFG0 */ |
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| 179 | #define TPC0_QM_PQ_CFG0_RESERVED_SHIFT 0 |
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| 180 | #define TPC0_QM_PQ_CFG0_RESERVED_MASK 0x1 |
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| 181 | |
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| 182 | /* TPC0_QM_PQ_CFG1 */ |
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| 183 | #define TPC0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 |
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| 184 | #define TPC0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFFFF |
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| 185 | #define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 |
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| 186 | #define TPC0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 |
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| 187 | |
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| 188 | /* TPC0_QM_PQ_ARUSER */ |
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| 189 | #define TPC0_QM_PQ_ARUSER_NOSNOOP_SHIFT 0 |
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| 190 | #define TPC0_QM_PQ_ARUSER_NOSNOOP_MASK 0x1 |
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| 191 | #define TPC0_QM_PQ_ARUSER_WORD_SHIFT 1 |
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| 192 | #define TPC0_QM_PQ_ARUSER_WORD_MASK 0x2 |
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| 193 | |
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| 194 | /* TPC0_QM_PQ_PUSH0 */ |
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| 195 | #define TPC0_QM_PQ_PUSH0_PTR_LO_SHIFT 0 |
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| 196 | #define TPC0_QM_PQ_PUSH0_PTR_LO_MASK 0xFFFFFFFF |
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| 197 | |
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| 198 | /* TPC0_QM_PQ_PUSH1 */ |
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| 199 | #define TPC0_QM_PQ_PUSH1_PTR_HI_SHIFT 0 |
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| 200 | #define TPC0_QM_PQ_PUSH1_PTR_HI_MASK 0xFFFFFFFF |
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| 201 | |
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| 202 | /* TPC0_QM_PQ_PUSH2 */ |
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| 203 | #define TPC0_QM_PQ_PUSH2_TSIZE_SHIFT 0 |
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| 204 | #define TPC0_QM_PQ_PUSH2_TSIZE_MASK 0xFFFFFFFF |
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| 205 | |
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| 206 | /* TPC0_QM_PQ_PUSH3 */ |
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| 207 | #define TPC0_QM_PQ_PUSH3_RPT_SHIFT 0 |
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| 208 | #define TPC0_QM_PQ_PUSH3_RPT_MASK 0xFFFF |
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| 209 | #define TPC0_QM_PQ_PUSH3_CTL_SHIFT 16 |
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| 210 | #define TPC0_QM_PQ_PUSH3_CTL_MASK 0xFFFF0000 |
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| 211 | |
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| 212 | /* TPC0_QM_PQ_STS0 */ |
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| 213 | #define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT 0 |
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| 214 | #define TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK 0xFFFF |
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| 215 | #define TPC0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT 16 |
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| 216 | #define TPC0_QM_PQ_STS0_PQ_FREE_CNT_MASK 0xFFFF0000 |
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| 217 | |
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| 218 | /* TPC0_QM_PQ_STS1 */ |
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| 219 | #define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT 0 |
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| 220 | #define TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK 0xFFFF |
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| 221 | #define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT 30 |
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| 222 | #define TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK 0x40000000 |
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| 223 | #define TPC0_QM_PQ_STS1_PQ_BUSY_SHIFT 31 |
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| 224 | #define TPC0_QM_PQ_STS1_PQ_BUSY_MASK 0x80000000 |
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| 225 | |
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| 226 | /* TPC0_QM_PQ_RD_RATE_LIM_EN */ |
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| 227 | #define TPC0_QM_PQ_RD_RATE_LIM_EN_VAL_SHIFT 0 |
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| 228 | #define TPC0_QM_PQ_RD_RATE_LIM_EN_VAL_MASK 0x1 |
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| 229 | |
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| 230 | /* TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN */ |
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| 231 | #define TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 |
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| 232 | #define TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF |
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| 233 | |
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| 234 | /* TPC0_QM_PQ_RD_RATE_LIM_SAT */ |
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| 235 | #define TPC0_QM_PQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 |
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| 236 | #define TPC0_QM_PQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF |
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| 237 | |
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| 238 | /* TPC0_QM_PQ_RD_RATE_LIM_TOUT */ |
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| 239 | #define TPC0_QM_PQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 |
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| 240 | #define TPC0_QM_PQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF |
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| 241 | |
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| 242 | /* TPC0_QM_CQ_CFG0 */ |
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| 243 | #define TPC0_QM_CQ_CFG0_RESERVED_SHIFT 0 |
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| 244 | #define TPC0_QM_CQ_CFG0_RESERVED_MASK 0x1 |
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| 245 | |
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| 246 | /* TPC0_QM_CQ_CFG1 */ |
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| 247 | #define TPC0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 |
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| 248 | #define TPC0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFFFF |
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| 249 | #define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 |
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| 250 | #define TPC0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFFFF0000 |
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| 251 | |
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| 252 | /* TPC0_QM_CQ_ARUSER */ |
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| 253 | #define TPC0_QM_CQ_ARUSER_NOSNOOP_SHIFT 0 |
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| 254 | #define TPC0_QM_CQ_ARUSER_NOSNOOP_MASK 0x1 |
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| 255 | #define TPC0_QM_CQ_ARUSER_WORD_SHIFT 1 |
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| 256 | #define TPC0_QM_CQ_ARUSER_WORD_MASK 0x2 |
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| 257 | |
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| 258 | /* TPC0_QM_CQ_PTR_LO */ |
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| 259 | #define TPC0_QM_CQ_PTR_LO_VAL_SHIFT 0 |
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| 260 | #define TPC0_QM_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF |
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| 261 | |
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| 262 | /* TPC0_QM_CQ_PTR_HI */ |
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| 263 | #define TPC0_QM_CQ_PTR_HI_VAL_SHIFT 0 |
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| 264 | #define TPC0_QM_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF |
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| 265 | |
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| 266 | /* TPC0_QM_CQ_TSIZE */ |
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| 267 | #define TPC0_QM_CQ_TSIZE_VAL_SHIFT 0 |
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| 268 | #define TPC0_QM_CQ_TSIZE_VAL_MASK 0xFFFFFFFF |
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| 269 | |
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| 270 | /* TPC0_QM_CQ_CTL */ |
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| 271 | #define TPC0_QM_CQ_CTL_RPT_SHIFT 0 |
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| 272 | #define TPC0_QM_CQ_CTL_RPT_MASK 0xFFFF |
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| 273 | #define TPC0_QM_CQ_CTL_CTL_SHIFT 16 |
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| 274 | #define TPC0_QM_CQ_CTL_CTL_MASK 0xFFFF0000 |
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| 275 | |
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| 276 | /* TPC0_QM_CQ_PTR_LO_STS */ |
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| 277 | #define TPC0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 |
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| 278 | #define TPC0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF |
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| 279 | |
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| 280 | /* TPC0_QM_CQ_PTR_HI_STS */ |
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| 281 | #define TPC0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 |
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| 282 | #define TPC0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF |
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| 283 | |
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| 284 | /* TPC0_QM_CQ_TSIZE_STS */ |
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| 285 | #define TPC0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 |
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| 286 | #define TPC0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF |
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| 287 | |
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| 288 | /* TPC0_QM_CQ_CTL_STS */ |
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| 289 | #define TPC0_QM_CQ_CTL_STS_RPT_SHIFT 0 |
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| 290 | #define TPC0_QM_CQ_CTL_STS_RPT_MASK 0xFFFF |
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| 291 | #define TPC0_QM_CQ_CTL_STS_CTL_SHIFT 16 |
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| 292 | #define TPC0_QM_CQ_CTL_STS_CTL_MASK 0xFFFF0000 |
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| 293 | |
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| 294 | /* TPC0_QM_CQ_STS0 */ |
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| 295 | #define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT 0 |
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| 296 | #define TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK 0xFFFF |
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| 297 | #define TPC0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT 16 |
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| 298 | #define TPC0_QM_CQ_STS0_CQ_FREE_CNT_MASK 0xFFFF0000 |
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| 299 | |
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| 300 | /* TPC0_QM_CQ_STS1 */ |
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| 301 | #define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT 0 |
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| 302 | #define TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK 0xFFFF |
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| 303 | #define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT 30 |
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| 304 | #define TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK 0x40000000 |
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| 305 | #define TPC0_QM_CQ_STS1_CQ_BUSY_SHIFT 31 |
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| 306 | #define TPC0_QM_CQ_STS1_CQ_BUSY_MASK 0x80000000 |
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| 307 | |
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| 308 | /* TPC0_QM_CQ_RD_RATE_LIM_EN */ |
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| 309 | #define TPC0_QM_CQ_RD_RATE_LIM_EN_VAL_SHIFT 0 |
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| 310 | #define TPC0_QM_CQ_RD_RATE_LIM_EN_VAL_MASK 0x1 |
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| 311 | |
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| 312 | /* TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN */ |
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| 313 | #define TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT 0 |
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| 314 | #define TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK 0xFFFF |
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| 315 | |
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| 316 | /* TPC0_QM_CQ_RD_RATE_LIM_SAT */ |
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| 317 | #define TPC0_QM_CQ_RD_RATE_LIM_SAT_VAL_SHIFT 0 |
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| 318 | #define TPC0_QM_CQ_RD_RATE_LIM_SAT_VAL_MASK 0xFFFF |
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| 319 | |
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| 320 | /* TPC0_QM_CQ_RD_RATE_LIM_TOUT */ |
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| 321 | #define TPC0_QM_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT 0 |
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| 322 | #define TPC0_QM_CQ_RD_RATE_LIM_TOUT_VAL_MASK 0x7FFFFFFF |
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| 323 | |
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| 324 | /* TPC0_QM_CQ_IFIFO_CNT */ |
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| 325 | #define TPC0_QM_CQ_IFIFO_CNT_VAL_SHIFT 0 |
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| 326 | #define TPC0_QM_CQ_IFIFO_CNT_VAL_MASK 0x3 |
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| 327 | |
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| 328 | /* TPC0_QM_CP_MSG_BASE0_ADDR_LO */ |
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| 329 | #define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 |
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| 330 | #define TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF |
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| 331 | |
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| 332 | /* TPC0_QM_CP_MSG_BASE0_ADDR_HI */ |
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| 333 | #define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 |
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| 334 | #define TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF |
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| 335 | |
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| 336 | /* TPC0_QM_CP_MSG_BASE1_ADDR_LO */ |
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| 337 | #define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 |
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| 338 | #define TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF |
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| 339 | |
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| 340 | /* TPC0_QM_CP_MSG_BASE1_ADDR_HI */ |
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| 341 | #define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 |
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| 342 | #define TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF |
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| 343 | |
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| 344 | /* TPC0_QM_CP_MSG_BASE2_ADDR_LO */ |
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| 345 | #define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 |
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| 346 | #define TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF |
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| 347 | |
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| 348 | /* TPC0_QM_CP_MSG_BASE2_ADDR_HI */ |
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| 349 | #define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 |
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| 350 | #define TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF |
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| 351 | |
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| 352 | /* TPC0_QM_CP_MSG_BASE3_ADDR_LO */ |
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| 353 | #define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 |
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| 354 | #define TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF |
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| 355 | |
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| 356 | /* TPC0_QM_CP_MSG_BASE3_ADDR_HI */ |
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| 357 | #define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 |
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| 358 | #define TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF |
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| 359 | |
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| 360 | /* TPC0_QM_CP_LDMA_TSIZE_OFFSET */ |
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| 361 | #define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 |
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| 362 | #define TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFFFFFF |
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| 363 | |
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| 364 | /* TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ |
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| 365 | #define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 |
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| 366 | #define TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF |
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| 367 | |
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| 368 | /* TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET */ |
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| 369 | #define TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT 0 |
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| 370 | #define TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF |
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| 371 | |
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| 372 | /* TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ |
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| 373 | #define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 |
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| 374 | #define TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFFFFFF |
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| 375 | |
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| 376 | /* TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET */ |
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| 377 | #define TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT 0 |
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| 378 | #define TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK 0xFFFFFFFF |
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| 379 | |
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| 380 | /* TPC0_QM_CP_LDMA_COMMIT_OFFSET */ |
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| 381 | #define TPC0_QM_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT 0 |
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| 382 | #define TPC0_QM_CP_LDMA_COMMIT_OFFSET_VAL_MASK 0xFFFFFFFF |
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| 383 | |
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| 384 | /* TPC0_QM_CP_FENCE0_RDATA */ |
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| 385 | #define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 |
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| 386 | #define TPC0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF |
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| 387 | |
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| 388 | /* TPC0_QM_CP_FENCE1_RDATA */ |
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| 389 | #define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 |
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| 390 | #define TPC0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF |
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| 391 | |
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| 392 | /* TPC0_QM_CP_FENCE2_RDATA */ |
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| 393 | #define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 |
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| 394 | #define TPC0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF |
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| 395 | |
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| 396 | /* TPC0_QM_CP_FENCE3_RDATA */ |
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| 397 | #define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 |
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| 398 | #define TPC0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF |
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| 399 | |
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| 400 | /* TPC0_QM_CP_FENCE0_CNT */ |
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| 401 | #define TPC0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 |
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| 402 | #define TPC0_QM_CP_FENCE0_CNT_VAL_MASK 0xFF |
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| 403 | |
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| 404 | /* TPC0_QM_CP_FENCE1_CNT */ |
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| 405 | #define TPC0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 |
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| 406 | #define TPC0_QM_CP_FENCE1_CNT_VAL_MASK 0xFF |
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| 407 | |
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| 408 | /* TPC0_QM_CP_FENCE2_CNT */ |
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| 409 | #define TPC0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 |
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| 410 | #define TPC0_QM_CP_FENCE2_CNT_VAL_MASK 0xFF |
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| 411 | |
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| 412 | /* TPC0_QM_CP_FENCE3_CNT */ |
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| 413 | #define TPC0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 |
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| 414 | #define TPC0_QM_CP_FENCE3_CNT_VAL_MASK 0xFF |
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| 415 | |
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| 416 | /* TPC0_QM_CP_STS */ |
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| 417 | #define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 |
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| 418 | #define TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFFFF |
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| 419 | #define TPC0_QM_CP_STS_ERDY_SHIFT 16 |
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| 420 | #define TPC0_QM_CP_STS_ERDY_MASK 0x10000 |
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| 421 | #define TPC0_QM_CP_STS_RRDY_SHIFT 17 |
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| 422 | #define TPC0_QM_CP_STS_RRDY_MASK 0x20000 |
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| 423 | #define TPC0_QM_CP_STS_MRDY_SHIFT 18 |
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| 424 | #define TPC0_QM_CP_STS_MRDY_MASK 0x40000 |
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| 425 | #define TPC0_QM_CP_STS_SW_STOP_SHIFT 19 |
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| 426 | #define TPC0_QM_CP_STS_SW_STOP_MASK 0x80000 |
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| 427 | #define TPC0_QM_CP_STS_FENCE_ID_SHIFT 20 |
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| 428 | #define TPC0_QM_CP_STS_FENCE_ID_MASK 0x300000 |
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| 429 | #define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 22 |
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| 430 | #define TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x400000 |
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| 431 | |
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| 432 | /* TPC0_QM_CP_CURRENT_INST_LO */ |
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| 433 | #define TPC0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 |
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| 434 | #define TPC0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF |
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| 435 | |
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| 436 | /* TPC0_QM_CP_CURRENT_INST_HI */ |
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| 437 | #define TPC0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 |
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| 438 | #define TPC0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF |
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| 439 | |
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| 440 | /* TPC0_QM_CP_BARRIER_CFG */ |
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| 441 | #define TPC0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 |
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| 442 | #define TPC0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF |
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| 443 | |
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| 444 | /* TPC0_QM_CP_DBG_0 */ |
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| 445 | #define TPC0_QM_CP_DBG_0_VAL_SHIFT 0 |
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| 446 | #define TPC0_QM_CP_DBG_0_VAL_MASK 0xFF |
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| 447 | |
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| 448 | /* TPC0_QM_PQ_BUF_ADDR */ |
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| 449 | #define TPC0_QM_PQ_BUF_ADDR_VAL_SHIFT 0 |
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| 450 | #define TPC0_QM_PQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF |
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| 451 | |
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| 452 | /* TPC0_QM_PQ_BUF_RDATA */ |
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| 453 | #define TPC0_QM_PQ_BUF_RDATA_VAL_SHIFT 0 |
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| 454 | #define TPC0_QM_PQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF |
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| 455 | |
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| 456 | /* TPC0_QM_CQ_BUF_ADDR */ |
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| 457 | #define TPC0_QM_CQ_BUF_ADDR_VAL_SHIFT 0 |
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| 458 | #define TPC0_QM_CQ_BUF_ADDR_VAL_MASK 0xFFFFFFFF |
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| 459 | |
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| 460 | /* TPC0_QM_CQ_BUF_RDATA */ |
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| 461 | #define TPC0_QM_CQ_BUF_RDATA_VAL_SHIFT 0 |
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| 462 | #define TPC0_QM_CQ_BUF_RDATA_VAL_MASK 0xFFFFFFFF |
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| 463 | |
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| 464 | #endif /* ASIC_REG_TPC0_QM_MASKS_H_ */ |
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| 465 | |
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