| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2018 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_DMA_NRTR_REGS_H_ |
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| 14 | #define ASIC_REG_DMA_NRTR_REGS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * DMA_NRTR (Prototype: IF_NRTR) |
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| 19 | ***************************************** |
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| 20 | */ |
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| 21 | |
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| 22 | #define mmDMA_NRTR_HBW_MAX_CRED 0x1C0100 |
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| 23 | |
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| 24 | #define mmDMA_NRTR_LBW_MAX_CRED 0x1C0120 |
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| 25 | |
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| 26 | #define mmDMA_NRTR_DBG_E_ARB 0x1C0300 |
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| 27 | |
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| 28 | #define mmDMA_NRTR_DBG_W_ARB 0x1C0304 |
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| 29 | |
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| 30 | #define mmDMA_NRTR_DBG_N_ARB 0x1C0308 |
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| 31 | |
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| 32 | #define mmDMA_NRTR_DBG_S_ARB 0x1C030C |
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| 33 | |
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| 34 | #define mmDMA_NRTR_DBG_L_ARB 0x1C0310 |
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| 35 | |
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| 36 | #define mmDMA_NRTR_DBG_E_ARB_MAX 0x1C0320 |
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| 37 | |
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| 38 | #define mmDMA_NRTR_DBG_W_ARB_MAX 0x1C0324 |
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| 39 | |
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| 40 | #define mmDMA_NRTR_DBG_N_ARB_MAX 0x1C0328 |
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| 41 | |
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| 42 | #define mmDMA_NRTR_DBG_S_ARB_MAX 0x1C032C |
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| 43 | |
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| 44 | #define mmDMA_NRTR_DBG_L_ARB_MAX 0x1C0330 |
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| 45 | |
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| 46 | #define mmDMA_NRTR_SPLIT_COEF_0 0x1C0400 |
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| 47 | |
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| 48 | #define mmDMA_NRTR_SPLIT_COEF_1 0x1C0404 |
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| 49 | |
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| 50 | #define mmDMA_NRTR_SPLIT_COEF_2 0x1C0408 |
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| 51 | |
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| 52 | #define mmDMA_NRTR_SPLIT_COEF_3 0x1C040C |
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| 53 | |
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| 54 | #define mmDMA_NRTR_SPLIT_COEF_4 0x1C0410 |
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| 55 | |
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| 56 | #define mmDMA_NRTR_SPLIT_COEF_5 0x1C0414 |
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| 57 | |
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| 58 | #define mmDMA_NRTR_SPLIT_COEF_6 0x1C0418 |
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| 59 | |
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| 60 | #define mmDMA_NRTR_SPLIT_COEF_7 0x1C041C |
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| 61 | |
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| 62 | #define mmDMA_NRTR_SPLIT_COEF_8 0x1C0420 |
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| 63 | |
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| 64 | #define mmDMA_NRTR_SPLIT_COEF_9 0x1C0424 |
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| 65 | |
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| 66 | #define mmDMA_NRTR_SPLIT_CFG 0x1C0440 |
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| 67 | |
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| 68 | #define mmDMA_NRTR_SPLIT_RD_SAT 0x1C0444 |
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| 69 | |
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| 70 | #define mmDMA_NRTR_SPLIT_RD_RST_TOKEN 0x1C0448 |
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| 71 | |
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| 72 | #define mmDMA_NRTR_SPLIT_RD_TIMEOUT_0 0x1C044C |
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| 73 | |
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| 74 | #define mmDMA_NRTR_SPLIT_RD_TIMEOUT_1 0x1C0450 |
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| 75 | |
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| 76 | #define mmDMA_NRTR_SPLIT_WR_SAT 0x1C0454 |
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| 77 | |
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| 78 | #define mmDMA_NRTR_WPLIT_WR_TST_TOLEN 0x1C0458 |
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| 79 | |
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| 80 | #define mmDMA_NRTR_SPLIT_WR_TIMEOUT_0 0x1C045C |
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| 81 | |
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| 82 | #define mmDMA_NRTR_SPLIT_WR_TIMEOUT_1 0x1C0460 |
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| 83 | |
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| 84 | #define mmDMA_NRTR_HBW_RANGE_HIT 0x1C0470 |
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| 85 | |
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| 86 | #define mmDMA_NRTR_HBW_RANGE_MASK_L_0 0x1C0480 |
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| 87 | |
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| 88 | #define mmDMA_NRTR_HBW_RANGE_MASK_L_1 0x1C0484 |
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| 89 | |
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| 90 | #define mmDMA_NRTR_HBW_RANGE_MASK_L_2 0x1C0488 |
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| 91 | |
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| 92 | #define mmDMA_NRTR_HBW_RANGE_MASK_L_3 0x1C048C |
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| 93 | |
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| 94 | #define mmDMA_NRTR_HBW_RANGE_MASK_L_4 0x1C0490 |
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| 95 | |
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| 96 | #define mmDMA_NRTR_HBW_RANGE_MASK_L_5 0x1C0494 |
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| 97 | |
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| 98 | #define mmDMA_NRTR_HBW_RANGE_MASK_L_6 0x1C0498 |
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| 99 | |
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| 100 | #define mmDMA_NRTR_HBW_RANGE_MASK_L_7 0x1C049C |
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| 101 | |
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| 102 | #define mmDMA_NRTR_HBW_RANGE_MASK_H_0 0x1C04A0 |
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| 103 | |
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| 104 | #define mmDMA_NRTR_HBW_RANGE_MASK_H_1 0x1C04A4 |
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| 105 | |
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| 106 | #define mmDMA_NRTR_HBW_RANGE_MASK_H_2 0x1C04A8 |
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| 107 | |
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| 108 | #define mmDMA_NRTR_HBW_RANGE_MASK_H_3 0x1C04AC |
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| 109 | |
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| 110 | #define mmDMA_NRTR_HBW_RANGE_MASK_H_4 0x1C04B0 |
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| 111 | |
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| 112 | #define mmDMA_NRTR_HBW_RANGE_MASK_H_5 0x1C04B4 |
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| 113 | |
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| 114 | #define mmDMA_NRTR_HBW_RANGE_MASK_H_6 0x1C04B8 |
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| 115 | |
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| 116 | #define mmDMA_NRTR_HBW_RANGE_MASK_H_7 0x1C04BC |
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| 117 | |
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| 118 | #define mmDMA_NRTR_HBW_RANGE_BASE_L_0 0x1C04C0 |
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| 119 | |
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| 120 | #define mmDMA_NRTR_HBW_RANGE_BASE_L_1 0x1C04C4 |
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| 121 | |
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| 122 | #define mmDMA_NRTR_HBW_RANGE_BASE_L_2 0x1C04C8 |
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| 123 | |
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| 124 | #define mmDMA_NRTR_HBW_RANGE_BASE_L_3 0x1C04CC |
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| 125 | |
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| 126 | #define mmDMA_NRTR_HBW_RANGE_BASE_L_4 0x1C04D0 |
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| 127 | |
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| 128 | #define mmDMA_NRTR_HBW_RANGE_BASE_L_5 0x1C04D4 |
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| 129 | |
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| 130 | #define mmDMA_NRTR_HBW_RANGE_BASE_L_6 0x1C04D8 |
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| 131 | |
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| 132 | #define mmDMA_NRTR_HBW_RANGE_BASE_L_7 0x1C04DC |
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| 133 | |
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| 134 | #define mmDMA_NRTR_HBW_RANGE_BASE_H_0 0x1C04E0 |
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| 135 | |
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| 136 | #define mmDMA_NRTR_HBW_RANGE_BASE_H_1 0x1C04E4 |
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| 137 | |
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| 138 | #define mmDMA_NRTR_HBW_RANGE_BASE_H_2 0x1C04E8 |
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| 139 | |
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| 140 | #define mmDMA_NRTR_HBW_RANGE_BASE_H_3 0x1C04EC |
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| 141 | |
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| 142 | #define mmDMA_NRTR_HBW_RANGE_BASE_H_4 0x1C04F0 |
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| 143 | |
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| 144 | #define mmDMA_NRTR_HBW_RANGE_BASE_H_5 0x1C04F4 |
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| 145 | |
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| 146 | #define mmDMA_NRTR_HBW_RANGE_BASE_H_6 0x1C04F8 |
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| 147 | |
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| 148 | #define mmDMA_NRTR_HBW_RANGE_BASE_H_7 0x1C04FC |
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| 149 | |
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| 150 | #define mmDMA_NRTR_LBW_RANGE_HIT 0x1C0500 |
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| 151 | |
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| 152 | #define mmDMA_NRTR_LBW_RANGE_MASK_0 0x1C0510 |
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| 153 | |
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| 154 | #define mmDMA_NRTR_LBW_RANGE_MASK_1 0x1C0514 |
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| 155 | |
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| 156 | #define mmDMA_NRTR_LBW_RANGE_MASK_2 0x1C0518 |
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| 157 | |
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| 158 | #define mmDMA_NRTR_LBW_RANGE_MASK_3 0x1C051C |
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| 159 | |
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| 160 | #define mmDMA_NRTR_LBW_RANGE_MASK_4 0x1C0520 |
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| 161 | |
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| 162 | #define mmDMA_NRTR_LBW_RANGE_MASK_5 0x1C0524 |
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| 163 | |
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| 164 | #define mmDMA_NRTR_LBW_RANGE_MASK_6 0x1C0528 |
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| 165 | |
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| 166 | #define mmDMA_NRTR_LBW_RANGE_MASK_7 0x1C052C |
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| 167 | |
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| 168 | #define mmDMA_NRTR_LBW_RANGE_MASK_8 0x1C0530 |
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| 169 | |
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| 170 | #define mmDMA_NRTR_LBW_RANGE_MASK_9 0x1C0534 |
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| 171 | |
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| 172 | #define mmDMA_NRTR_LBW_RANGE_MASK_10 0x1C0538 |
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| 173 | |
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| 174 | #define mmDMA_NRTR_LBW_RANGE_MASK_11 0x1C053C |
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| 175 | |
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| 176 | #define mmDMA_NRTR_LBW_RANGE_MASK_12 0x1C0540 |
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| 177 | |
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| 178 | #define mmDMA_NRTR_LBW_RANGE_MASK_13 0x1C0544 |
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| 179 | |
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| 180 | #define mmDMA_NRTR_LBW_RANGE_MASK_14 0x1C0548 |
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| 181 | |
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| 182 | #define mmDMA_NRTR_LBW_RANGE_MASK_15 0x1C054C |
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| 183 | |
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| 184 | #define mmDMA_NRTR_LBW_RANGE_BASE_0 0x1C0550 |
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| 185 | |
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| 186 | #define mmDMA_NRTR_LBW_RANGE_BASE_1 0x1C0554 |
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| 187 | |
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| 188 | #define mmDMA_NRTR_LBW_RANGE_BASE_2 0x1C0558 |
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| 189 | |
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| 190 | #define mmDMA_NRTR_LBW_RANGE_BASE_3 0x1C055C |
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| 191 | |
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| 192 | #define mmDMA_NRTR_LBW_RANGE_BASE_4 0x1C0560 |
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| 193 | |
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| 194 | #define mmDMA_NRTR_LBW_RANGE_BASE_5 0x1C0564 |
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| 195 | |
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| 196 | #define mmDMA_NRTR_LBW_RANGE_BASE_6 0x1C0568 |
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| 197 | |
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| 198 | #define mmDMA_NRTR_LBW_RANGE_BASE_7 0x1C056C |
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| 199 | |
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| 200 | #define mmDMA_NRTR_LBW_RANGE_BASE_8 0x1C0570 |
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| 201 | |
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| 202 | #define mmDMA_NRTR_LBW_RANGE_BASE_9 0x1C0574 |
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| 203 | |
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| 204 | #define mmDMA_NRTR_LBW_RANGE_BASE_10 0x1C0578 |
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| 205 | |
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| 206 | #define mmDMA_NRTR_LBW_RANGE_BASE_11 0x1C057C |
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| 207 | |
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| 208 | #define mmDMA_NRTR_LBW_RANGE_BASE_12 0x1C0580 |
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| 209 | |
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| 210 | #define mmDMA_NRTR_LBW_RANGE_BASE_13 0x1C0584 |
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| 211 | |
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| 212 | #define mmDMA_NRTR_LBW_RANGE_BASE_14 0x1C0588 |
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| 213 | |
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| 214 | #define mmDMA_NRTR_LBW_RANGE_BASE_15 0x1C058C |
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| 215 | |
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| 216 | #define mmDMA_NRTR_RGLTR 0x1C0590 |
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| 217 | |
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| 218 | #define mmDMA_NRTR_RGLTR_WR_RESULT 0x1C0594 |
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| 219 | |
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| 220 | #define mmDMA_NRTR_RGLTR_RD_RESULT 0x1C0598 |
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| 221 | |
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| 222 | #define mmDMA_NRTR_SCRAMB_EN 0x1C0600 |
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| 223 | |
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| 224 | #define mmDMA_NRTR_NON_LIN_SCRAMB 0x1C0604 |
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| 225 | |
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| 226 | #endif /* ASIC_REG_DMA_NRTR_REGS_H_ */ |
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| 227 | |
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