1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2018 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8/************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
12
13#ifndef ASIC_REG_TPC0_QM_REGS_H_
14#define ASIC_REG_TPC0_QM_REGS_H_
15
16/*
17 *****************************************
18 * TPC0_QM (Prototype: QMAN)
19 *****************************************
20 */
21
22#define mmTPC0_QM_GLBL_CFG0 0xE08000
23
24#define mmTPC0_QM_GLBL_CFG1 0xE08004
25
26#define mmTPC0_QM_GLBL_PROT 0xE08008
27
28#define mmTPC0_QM_GLBL_ERR_CFG 0xE0800C
29
30#define mmTPC0_QM_GLBL_SECURE_PROPS_0 0xE08010
31
32#define mmTPC0_QM_GLBL_SECURE_PROPS_1 0xE08014
33
34#define mmTPC0_QM_GLBL_SECURE_PROPS_2 0xE08018
35
36#define mmTPC0_QM_GLBL_SECURE_PROPS_3 0xE0801C
37
38#define mmTPC0_QM_GLBL_SECURE_PROPS_4 0xE08020
39
40#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_0 0xE08024
41
42#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_1 0xE08028
43
44#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_2 0xE0802C
45
46#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_3 0xE08030
47
48#define mmTPC0_QM_GLBL_NON_SECURE_PROPS_4 0xE08034
49
50#define mmTPC0_QM_GLBL_STS0 0xE08038
51
52#define mmTPC0_QM_GLBL_STS1_0 0xE08040
53
54#define mmTPC0_QM_GLBL_STS1_1 0xE08044
55
56#define mmTPC0_QM_GLBL_STS1_2 0xE08048
57
58#define mmTPC0_QM_GLBL_STS1_3 0xE0804C
59
60#define mmTPC0_QM_GLBL_STS1_4 0xE08050
61
62#define mmTPC0_QM_GLBL_MSG_EN_0 0xE08054
63
64#define mmTPC0_QM_GLBL_MSG_EN_1 0xE08058
65
66#define mmTPC0_QM_GLBL_MSG_EN_2 0xE0805C
67
68#define mmTPC0_QM_GLBL_MSG_EN_3 0xE08060
69
70#define mmTPC0_QM_GLBL_MSG_EN_4 0xE08068
71
72#define mmTPC0_QM_PQ_BASE_LO_0 0xE08070
73
74#define mmTPC0_QM_PQ_BASE_LO_1 0xE08074
75
76#define mmTPC0_QM_PQ_BASE_LO_2 0xE08078
77
78#define mmTPC0_QM_PQ_BASE_LO_3 0xE0807C
79
80#define mmTPC0_QM_PQ_BASE_HI_0 0xE08080
81
82#define mmTPC0_QM_PQ_BASE_HI_1 0xE08084
83
84#define mmTPC0_QM_PQ_BASE_HI_2 0xE08088
85
86#define mmTPC0_QM_PQ_BASE_HI_3 0xE0808C
87
88#define mmTPC0_QM_PQ_SIZE_0 0xE08090
89
90#define mmTPC0_QM_PQ_SIZE_1 0xE08094
91
92#define mmTPC0_QM_PQ_SIZE_2 0xE08098
93
94#define mmTPC0_QM_PQ_SIZE_3 0xE0809C
95
96#define mmTPC0_QM_PQ_PI_0 0xE080A0
97
98#define mmTPC0_QM_PQ_PI_1 0xE080A4
99
100#define mmTPC0_QM_PQ_PI_2 0xE080A8
101
102#define mmTPC0_QM_PQ_PI_3 0xE080AC
103
104#define mmTPC0_QM_PQ_CI_0 0xE080B0
105
106#define mmTPC0_QM_PQ_CI_1 0xE080B4
107
108#define mmTPC0_QM_PQ_CI_2 0xE080B8
109
110#define mmTPC0_QM_PQ_CI_3 0xE080BC
111
112#define mmTPC0_QM_PQ_CFG0_0 0xE080C0
113
114#define mmTPC0_QM_PQ_CFG0_1 0xE080C4
115
116#define mmTPC0_QM_PQ_CFG0_2 0xE080C8
117
118#define mmTPC0_QM_PQ_CFG0_3 0xE080CC
119
120#define mmTPC0_QM_PQ_CFG1_0 0xE080D0
121
122#define mmTPC0_QM_PQ_CFG1_1 0xE080D4
123
124#define mmTPC0_QM_PQ_CFG1_2 0xE080D8
125
126#define mmTPC0_QM_PQ_CFG1_3 0xE080DC
127
128#define mmTPC0_QM_PQ_ARUSER_31_11_0 0xE080E0
129
130#define mmTPC0_QM_PQ_ARUSER_31_11_1 0xE080E4
131
132#define mmTPC0_QM_PQ_ARUSER_31_11_2 0xE080E8
133
134#define mmTPC0_QM_PQ_ARUSER_31_11_3 0xE080EC
135
136#define mmTPC0_QM_PQ_STS0_0 0xE080F0
137
138#define mmTPC0_QM_PQ_STS0_1 0xE080F4
139
140#define mmTPC0_QM_PQ_STS0_2 0xE080F8
141
142#define mmTPC0_QM_PQ_STS0_3 0xE080FC
143
144#define mmTPC0_QM_PQ_STS1_0 0xE08100
145
146#define mmTPC0_QM_PQ_STS1_1 0xE08104
147
148#define mmTPC0_QM_PQ_STS1_2 0xE08108
149
150#define mmTPC0_QM_PQ_STS1_3 0xE0810C
151
152#define mmTPC0_QM_CQ_CFG0_0 0xE08110
153
154#define mmTPC0_QM_CQ_CFG0_1 0xE08114
155
156#define mmTPC0_QM_CQ_CFG0_2 0xE08118
157
158#define mmTPC0_QM_CQ_CFG0_3 0xE0811C
159
160#define mmTPC0_QM_CQ_CFG0_4 0xE08120
161
162#define mmTPC0_QM_CQ_CFG1_0 0xE08124
163
164#define mmTPC0_QM_CQ_CFG1_1 0xE08128
165
166#define mmTPC0_QM_CQ_CFG1_2 0xE0812C
167
168#define mmTPC0_QM_CQ_CFG1_3 0xE08130
169
170#define mmTPC0_QM_CQ_CFG1_4 0xE08134
171
172#define mmTPC0_QM_CQ_ARUSER_31_11_0 0xE08138
173
174#define mmTPC0_QM_CQ_ARUSER_31_11_1 0xE0813C
175
176#define mmTPC0_QM_CQ_ARUSER_31_11_2 0xE08140
177
178#define mmTPC0_QM_CQ_ARUSER_31_11_3 0xE08144
179
180#define mmTPC0_QM_CQ_ARUSER_31_11_4 0xE08148
181
182#define mmTPC0_QM_CQ_STS0_0 0xE0814C
183
184#define mmTPC0_QM_CQ_STS0_1 0xE08150
185
186#define mmTPC0_QM_CQ_STS0_2 0xE08154
187
188#define mmTPC0_QM_CQ_STS0_3 0xE08158
189
190#define mmTPC0_QM_CQ_STS0_4 0xE0815C
191
192#define mmTPC0_QM_CQ_STS1_0 0xE08160
193
194#define mmTPC0_QM_CQ_STS1_1 0xE08164
195
196#define mmTPC0_QM_CQ_STS1_2 0xE08168
197
198#define mmTPC0_QM_CQ_STS1_3 0xE0816C
199
200#define mmTPC0_QM_CQ_STS1_4 0xE08170
201
202#define mmTPC0_QM_CQ_PTR_LO_0 0xE08174
203
204#define mmTPC0_QM_CQ_PTR_HI_0 0xE08178
205
206#define mmTPC0_QM_CQ_TSIZE_0 0xE0817C
207
208#define mmTPC0_QM_CQ_CTL_0 0xE08180
209
210#define mmTPC0_QM_CQ_PTR_LO_1 0xE08184
211
212#define mmTPC0_QM_CQ_PTR_HI_1 0xE08188
213
214#define mmTPC0_QM_CQ_TSIZE_1 0xE0818C
215
216#define mmTPC0_QM_CQ_CTL_1 0xE08190
217
218#define mmTPC0_QM_CQ_PTR_LO_2 0xE08194
219
220#define mmTPC0_QM_CQ_PTR_HI_2 0xE08198
221
222#define mmTPC0_QM_CQ_TSIZE_2 0xE0819C
223
224#define mmTPC0_QM_CQ_CTL_2 0xE081A0
225
226#define mmTPC0_QM_CQ_PTR_LO_3 0xE081A4
227
228#define mmTPC0_QM_CQ_PTR_HI_3 0xE081A8
229
230#define mmTPC0_QM_CQ_TSIZE_3 0xE081AC
231
232#define mmTPC0_QM_CQ_CTL_3 0xE081B0
233
234#define mmTPC0_QM_CQ_PTR_LO_4 0xE081B4
235
236#define mmTPC0_QM_CQ_PTR_HI_4 0xE081B8
237
238#define mmTPC0_QM_CQ_TSIZE_4 0xE081BC
239
240#define mmTPC0_QM_CQ_CTL_4 0xE081C0
241
242#define mmTPC0_QM_CQ_PTR_LO_STS_0 0xE081C4
243
244#define mmTPC0_QM_CQ_PTR_LO_STS_1 0xE081C8
245
246#define mmTPC0_QM_CQ_PTR_LO_STS_2 0xE081CC
247
248#define mmTPC0_QM_CQ_PTR_LO_STS_3 0xE081D0
249
250#define mmTPC0_QM_CQ_PTR_LO_STS_4 0xE081D4
251
252#define mmTPC0_QM_CQ_PTR_HI_STS_0 0xE081D8
253
254#define mmTPC0_QM_CQ_PTR_HI_STS_1 0xE081DC
255
256#define mmTPC0_QM_CQ_PTR_HI_STS_2 0xE081E0
257
258#define mmTPC0_QM_CQ_PTR_HI_STS_3 0xE081E4
259
260#define mmTPC0_QM_CQ_PTR_HI_STS_4 0xE081E8
261
262#define mmTPC0_QM_CQ_TSIZE_STS_0 0xE081EC
263
264#define mmTPC0_QM_CQ_TSIZE_STS_1 0xE081F0
265
266#define mmTPC0_QM_CQ_TSIZE_STS_2 0xE081F4
267
268#define mmTPC0_QM_CQ_TSIZE_STS_3 0xE081F8
269
270#define mmTPC0_QM_CQ_TSIZE_STS_4 0xE081FC
271
272#define mmTPC0_QM_CQ_CTL_STS_0 0xE08200
273
274#define mmTPC0_QM_CQ_CTL_STS_1 0xE08204
275
276#define mmTPC0_QM_CQ_CTL_STS_2 0xE08208
277
278#define mmTPC0_QM_CQ_CTL_STS_3 0xE0820C
279
280#define mmTPC0_QM_CQ_CTL_STS_4 0xE08210
281
282#define mmTPC0_QM_CQ_IFIFO_CNT_0 0xE08214
283
284#define mmTPC0_QM_CQ_IFIFO_CNT_1 0xE08218
285
286#define mmTPC0_QM_CQ_IFIFO_CNT_2 0xE0821C
287
288#define mmTPC0_QM_CQ_IFIFO_CNT_3 0xE08220
289
290#define mmTPC0_QM_CQ_IFIFO_CNT_4 0xE08224
291
292#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_0 0xE08228
293
294#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_1 0xE0822C
295
296#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_2 0xE08230
297
298#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_3 0xE08234
299
300#define mmTPC0_QM_CP_MSG_BASE0_ADDR_LO_4 0xE08238
301
302#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_0 0xE0823C
303
304#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_1 0xE08240
305
306#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_2 0xE08244
307
308#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_3 0xE08248
309
310#define mmTPC0_QM_CP_MSG_BASE0_ADDR_HI_4 0xE0824C
311
312#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_0 0xE08250
313
314#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_1 0xE08254
315
316#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_2 0xE08258
317
318#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_3 0xE0825C
319
320#define mmTPC0_QM_CP_MSG_BASE1_ADDR_LO_4 0xE08260
321
322#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_0 0xE08264
323
324#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_1 0xE08268
325
326#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_2 0xE0826C
327
328#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_3 0xE08270
329
330#define mmTPC0_QM_CP_MSG_BASE1_ADDR_HI_4 0xE08274
331
332#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_0 0xE08278
333
334#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_1 0xE0827C
335
336#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_2 0xE08280
337
338#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_3 0xE08284
339
340#define mmTPC0_QM_CP_MSG_BASE2_ADDR_LO_4 0xE08288
341
342#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_0 0xE0828C
343
344#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_1 0xE08290
345
346#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_2 0xE08294
347
348#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_3 0xE08298
349
350#define mmTPC0_QM_CP_MSG_BASE2_ADDR_HI_4 0xE0829C
351
352#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_0 0xE082A0
353
354#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_1 0xE082A4
355
356#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_2 0xE082A8
357
358#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_3 0xE082AC
359
360#define mmTPC0_QM_CP_MSG_BASE3_ADDR_LO_4 0xE082B0
361
362#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_0 0xE082B4
363
364#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_1 0xE082B8
365
366#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_2 0xE082BC
367
368#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_3 0xE082C0
369
370#define mmTPC0_QM_CP_MSG_BASE3_ADDR_HI_4 0xE082C4
371
372#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_0 0xE082C8
373
374#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_1 0xE082CC
375
376#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_2 0xE082D0
377
378#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_3 0xE082D4
379
380#define mmTPC0_QM_CP_LDMA_TSIZE_OFFSET_4 0xE082D8
381
382#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xE082E0
383
384#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xE082E4
385
386#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xE082E8
387
388#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xE082EC
389
390#define mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xE082F0
391
392#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0xE082F4
393
394#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0xE082F8
395
396#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0xE082FC
397
398#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0xE08300
399
400#define mmTPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0xE08304
401
402#define mmTPC0_QM_CP_FENCE0_RDATA_0 0xE08308
403
404#define mmTPC0_QM_CP_FENCE0_RDATA_1 0xE0830C
405
406#define mmTPC0_QM_CP_FENCE0_RDATA_2 0xE08310
407
408#define mmTPC0_QM_CP_FENCE0_RDATA_3 0xE08314
409
410#define mmTPC0_QM_CP_FENCE0_RDATA_4 0xE08318
411
412#define mmTPC0_QM_CP_FENCE1_RDATA_0 0xE0831C
413
414#define mmTPC0_QM_CP_FENCE1_RDATA_1 0xE08320
415
416#define mmTPC0_QM_CP_FENCE1_RDATA_2 0xE08324
417
418#define mmTPC0_QM_CP_FENCE1_RDATA_3 0xE08328
419
420#define mmTPC0_QM_CP_FENCE1_RDATA_4 0xE0832C
421
422#define mmTPC0_QM_CP_FENCE2_RDATA_0 0xE08330
423
424#define mmTPC0_QM_CP_FENCE2_RDATA_1 0xE08334
425
426#define mmTPC0_QM_CP_FENCE2_RDATA_2 0xE08338
427
428#define mmTPC0_QM_CP_FENCE2_RDATA_3 0xE0833C
429
430#define mmTPC0_QM_CP_FENCE2_RDATA_4 0xE08340
431
432#define mmTPC0_QM_CP_FENCE3_RDATA_0 0xE08344
433
434#define mmTPC0_QM_CP_FENCE3_RDATA_1 0xE08348
435
436#define mmTPC0_QM_CP_FENCE3_RDATA_2 0xE0834C
437
438#define mmTPC0_QM_CP_FENCE3_RDATA_3 0xE08350
439
440#define mmTPC0_QM_CP_FENCE3_RDATA_4 0xE08354
441
442#define mmTPC0_QM_CP_FENCE0_CNT_0 0xE08358
443
444#define mmTPC0_QM_CP_FENCE0_CNT_1 0xE0835C
445
446#define mmTPC0_QM_CP_FENCE0_CNT_2 0xE08360
447
448#define mmTPC0_QM_CP_FENCE0_CNT_3 0xE08364
449
450#define mmTPC0_QM_CP_FENCE0_CNT_4 0xE08368
451
452#define mmTPC0_QM_CP_FENCE1_CNT_0 0xE0836C
453
454#define mmTPC0_QM_CP_FENCE1_CNT_1 0xE08370
455
456#define mmTPC0_QM_CP_FENCE1_CNT_2 0xE08374
457
458#define mmTPC0_QM_CP_FENCE1_CNT_3 0xE08378
459
460#define mmTPC0_QM_CP_FENCE1_CNT_4 0xE0837C
461
462#define mmTPC0_QM_CP_FENCE2_CNT_0 0xE08380
463
464#define mmTPC0_QM_CP_FENCE2_CNT_1 0xE08384
465
466#define mmTPC0_QM_CP_FENCE2_CNT_2 0xE08388
467
468#define mmTPC0_QM_CP_FENCE2_CNT_3 0xE0838C
469
470#define mmTPC0_QM_CP_FENCE2_CNT_4 0xE08390
471
472#define mmTPC0_QM_CP_FENCE3_CNT_0 0xE08394
473
474#define mmTPC0_QM_CP_FENCE3_CNT_1 0xE08398
475
476#define mmTPC0_QM_CP_FENCE3_CNT_2 0xE0839C
477
478#define mmTPC0_QM_CP_FENCE3_CNT_3 0xE083A0
479
480#define mmTPC0_QM_CP_FENCE3_CNT_4 0xE083A4
481
482#define mmTPC0_QM_CP_STS_0 0xE083A8
483
484#define mmTPC0_QM_CP_STS_1 0xE083AC
485
486#define mmTPC0_QM_CP_STS_2 0xE083B0
487
488#define mmTPC0_QM_CP_STS_3 0xE083B4
489
490#define mmTPC0_QM_CP_STS_4 0xE083B8
491
492#define mmTPC0_QM_CP_CURRENT_INST_LO_0 0xE083BC
493
494#define mmTPC0_QM_CP_CURRENT_INST_LO_1 0xE083C0
495
496#define mmTPC0_QM_CP_CURRENT_INST_LO_2 0xE083C4
497
498#define mmTPC0_QM_CP_CURRENT_INST_LO_3 0xE083C8
499
500#define mmTPC0_QM_CP_CURRENT_INST_LO_4 0xE083CC
501
502#define mmTPC0_QM_CP_CURRENT_INST_HI_0 0xE083D0
503
504#define mmTPC0_QM_CP_CURRENT_INST_HI_1 0xE083D4
505
506#define mmTPC0_QM_CP_CURRENT_INST_HI_2 0xE083D8
507
508#define mmTPC0_QM_CP_CURRENT_INST_HI_3 0xE083DC
509
510#define mmTPC0_QM_CP_CURRENT_INST_HI_4 0xE083E0
511
512#define mmTPC0_QM_CP_BARRIER_CFG_0 0xE083F4
513
514#define mmTPC0_QM_CP_BARRIER_CFG_1 0xE083F8
515
516#define mmTPC0_QM_CP_BARRIER_CFG_2 0xE083FC
517
518#define mmTPC0_QM_CP_BARRIER_CFG_3 0xE08400
519
520#define mmTPC0_QM_CP_BARRIER_CFG_4 0xE08404
521
522#define mmTPC0_QM_CP_DBG_0_0 0xE08408
523
524#define mmTPC0_QM_CP_DBG_0_1 0xE0840C
525
526#define mmTPC0_QM_CP_DBG_0_2 0xE08410
527
528#define mmTPC0_QM_CP_DBG_0_3 0xE08414
529
530#define mmTPC0_QM_CP_DBG_0_4 0xE08418
531
532#define mmTPC0_QM_CP_ARUSER_31_11_0 0xE0841C
533
534#define mmTPC0_QM_CP_ARUSER_31_11_1 0xE08420
535
536#define mmTPC0_QM_CP_ARUSER_31_11_2 0xE08424
537
538#define mmTPC0_QM_CP_ARUSER_31_11_3 0xE08428
539
540#define mmTPC0_QM_CP_ARUSER_31_11_4 0xE0842C
541
542#define mmTPC0_QM_CP_AWUSER_31_11_0 0xE08430
543
544#define mmTPC0_QM_CP_AWUSER_31_11_1 0xE08434
545
546#define mmTPC0_QM_CP_AWUSER_31_11_2 0xE08438
547
548#define mmTPC0_QM_CP_AWUSER_31_11_3 0xE0843C
549
550#define mmTPC0_QM_CP_AWUSER_31_11_4 0xE08440
551
552#define mmTPC0_QM_ARB_CFG_0 0xE08A00
553
554#define mmTPC0_QM_ARB_CHOISE_Q_PUSH 0xE08A04
555
556#define mmTPC0_QM_ARB_WRR_WEIGHT_0 0xE08A08
557
558#define mmTPC0_QM_ARB_WRR_WEIGHT_1 0xE08A0C
559
560#define mmTPC0_QM_ARB_WRR_WEIGHT_2 0xE08A10
561
562#define mmTPC0_QM_ARB_WRR_WEIGHT_3 0xE08A14
563
564#define mmTPC0_QM_ARB_CFG_1 0xE08A18
565
566#define mmTPC0_QM_ARB_MST_AVAIL_CRED_0 0xE08A20
567
568#define mmTPC0_QM_ARB_MST_AVAIL_CRED_1 0xE08A24
569
570#define mmTPC0_QM_ARB_MST_AVAIL_CRED_2 0xE08A28
571
572#define mmTPC0_QM_ARB_MST_AVAIL_CRED_3 0xE08A2C
573
574#define mmTPC0_QM_ARB_MST_AVAIL_CRED_4 0xE08A30
575
576#define mmTPC0_QM_ARB_MST_AVAIL_CRED_5 0xE08A34
577
578#define mmTPC0_QM_ARB_MST_AVAIL_CRED_6 0xE08A38
579
580#define mmTPC0_QM_ARB_MST_AVAIL_CRED_7 0xE08A3C
581
582#define mmTPC0_QM_ARB_MST_AVAIL_CRED_8 0xE08A40
583
584#define mmTPC0_QM_ARB_MST_AVAIL_CRED_9 0xE08A44
585
586#define mmTPC0_QM_ARB_MST_AVAIL_CRED_10 0xE08A48
587
588#define mmTPC0_QM_ARB_MST_AVAIL_CRED_11 0xE08A4C
589
590#define mmTPC0_QM_ARB_MST_AVAIL_CRED_12 0xE08A50
591
592#define mmTPC0_QM_ARB_MST_AVAIL_CRED_13 0xE08A54
593
594#define mmTPC0_QM_ARB_MST_AVAIL_CRED_14 0xE08A58
595
596#define mmTPC0_QM_ARB_MST_AVAIL_CRED_15 0xE08A5C
597
598#define mmTPC0_QM_ARB_MST_AVAIL_CRED_16 0xE08A60
599
600#define mmTPC0_QM_ARB_MST_AVAIL_CRED_17 0xE08A64
601
602#define mmTPC0_QM_ARB_MST_AVAIL_CRED_18 0xE08A68
603
604#define mmTPC0_QM_ARB_MST_AVAIL_CRED_19 0xE08A6C
605
606#define mmTPC0_QM_ARB_MST_AVAIL_CRED_20 0xE08A70
607
608#define mmTPC0_QM_ARB_MST_AVAIL_CRED_21 0xE08A74
609
610#define mmTPC0_QM_ARB_MST_AVAIL_CRED_22 0xE08A78
611
612#define mmTPC0_QM_ARB_MST_AVAIL_CRED_23 0xE08A7C
613
614#define mmTPC0_QM_ARB_MST_AVAIL_CRED_24 0xE08A80
615
616#define mmTPC0_QM_ARB_MST_AVAIL_CRED_25 0xE08A84
617
618#define mmTPC0_QM_ARB_MST_AVAIL_CRED_26 0xE08A88
619
620#define mmTPC0_QM_ARB_MST_AVAIL_CRED_27 0xE08A8C
621
622#define mmTPC0_QM_ARB_MST_AVAIL_CRED_28 0xE08A90
623
624#define mmTPC0_QM_ARB_MST_AVAIL_CRED_29 0xE08A94
625
626#define mmTPC0_QM_ARB_MST_AVAIL_CRED_30 0xE08A98
627
628#define mmTPC0_QM_ARB_MST_AVAIL_CRED_31 0xE08A9C
629
630#define mmTPC0_QM_ARB_MST_CRED_INC 0xE08AA0
631
632#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0xE08AA4
633
634#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0xE08AA8
635
636#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0xE08AAC
637
638#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0xE08AB0
639
640#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0xE08AB4
641
642#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0xE08AB8
643
644#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0xE08ABC
645
646#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0xE08AC0
647
648#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0xE08AC4
649
650#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0xE08AC8
651
652#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0xE08ACC
653
654#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0xE08AD0
655
656#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0xE08AD4
657
658#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0xE08AD8
659
660#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0xE08ADC
661
662#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0xE08AE0
663
664#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0xE08AE4
665
666#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0xE08AE8
667
668#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0xE08AEC
669
670#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0xE08AF0
671
672#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0xE08AF4
673
674#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0xE08AF8
675
676#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0xE08AFC
677
678#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0xE08B00
679
680#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0xE08B04
681
682#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0xE08B08
683
684#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0xE08B0C
685
686#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0xE08B10
687
688#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0xE08B14
689
690#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0xE08B18
691
692#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0xE08B1C
693
694#define mmTPC0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0xE08B20
695
696#define mmTPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0xE08B28
697
698#define mmTPC0_QM_ARB_MST_SLAVE_EN 0xE08B2C
699
700#define mmTPC0_QM_ARB_MST_QUIET_PER 0xE08B34
701
702#define mmTPC0_QM_ARB_SLV_CHOISE_WDT 0xE08B38
703
704#define mmTPC0_QM_ARB_SLV_ID 0xE08B3C
705
706#define mmTPC0_QM_ARB_MSG_MAX_INFLIGHT 0xE08B44
707
708#define mmTPC0_QM_ARB_MSG_AWUSER_31_11 0xE08B48
709
710#define mmTPC0_QM_ARB_MSG_AWUSER_SEC_PROP 0xE08B4C
711
712#define mmTPC0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0xE08B50
713
714#define mmTPC0_QM_ARB_BASE_LO 0xE08B54
715
716#define mmTPC0_QM_ARB_BASE_HI 0xE08B58
717
718#define mmTPC0_QM_ARB_STATE_STS 0xE08B80
719
720#define mmTPC0_QM_ARB_CHOISE_FULLNESS_STS 0xE08B84
721
722#define mmTPC0_QM_ARB_MSG_STS 0xE08B88
723
724#define mmTPC0_QM_ARB_SLV_CHOISE_Q_HEAD 0xE08B8C
725
726#define mmTPC0_QM_ARB_ERR_CAUSE 0xE08B9C
727
728#define mmTPC0_QM_ARB_ERR_MSG_EN 0xE08BA0
729
730#define mmTPC0_QM_ARB_ERR_STS_DRP 0xE08BA8
731
732#define mmTPC0_QM_ARB_MST_CRED_STS_0 0xE08BB0
733
734#define mmTPC0_QM_ARB_MST_CRED_STS_1 0xE08BB4
735
736#define mmTPC0_QM_ARB_MST_CRED_STS_2 0xE08BB8
737
738#define mmTPC0_QM_ARB_MST_CRED_STS_3 0xE08BBC
739
740#define mmTPC0_QM_ARB_MST_CRED_STS_4 0xE08BC0
741
742#define mmTPC0_QM_ARB_MST_CRED_STS_5 0xE08BC4
743
744#define mmTPC0_QM_ARB_MST_CRED_STS_6 0xE08BC8
745
746#define mmTPC0_QM_ARB_MST_CRED_STS_7 0xE08BCC
747
748#define mmTPC0_QM_ARB_MST_CRED_STS_8 0xE08BD0
749
750#define mmTPC0_QM_ARB_MST_CRED_STS_9 0xE08BD4
751
752#define mmTPC0_QM_ARB_MST_CRED_STS_10 0xE08BD8
753
754#define mmTPC0_QM_ARB_MST_CRED_STS_11 0xE08BDC
755
756#define mmTPC0_QM_ARB_MST_CRED_STS_12 0xE08BE0
757
758#define mmTPC0_QM_ARB_MST_CRED_STS_13 0xE08BE4
759
760#define mmTPC0_QM_ARB_MST_CRED_STS_14 0xE08BE8
761
762#define mmTPC0_QM_ARB_MST_CRED_STS_15 0xE08BEC
763
764#define mmTPC0_QM_ARB_MST_CRED_STS_16 0xE08BF0
765
766#define mmTPC0_QM_ARB_MST_CRED_STS_17 0xE08BF4
767
768#define mmTPC0_QM_ARB_MST_CRED_STS_18 0xE08BF8
769
770#define mmTPC0_QM_ARB_MST_CRED_STS_19 0xE08BFC
771
772#define mmTPC0_QM_ARB_MST_CRED_STS_20 0xE08C00
773
774#define mmTPC0_QM_ARB_MST_CRED_STS_21 0xE08C04
775
776#define mmTPC0_QM_ARB_MST_CRED_STS_22 0xE08C08
777
778#define mmTPC0_QM_ARB_MST_CRED_STS_23 0xE08C0C
779
780#define mmTPC0_QM_ARB_MST_CRED_STS_24 0xE08C10
781
782#define mmTPC0_QM_ARB_MST_CRED_STS_25 0xE08C14
783
784#define mmTPC0_QM_ARB_MST_CRED_STS_26 0xE08C18
785
786#define mmTPC0_QM_ARB_MST_CRED_STS_27 0xE08C1C
787
788#define mmTPC0_QM_ARB_MST_CRED_STS_28 0xE08C20
789
790#define mmTPC0_QM_ARB_MST_CRED_STS_29 0xE08C24
791
792#define mmTPC0_QM_ARB_MST_CRED_STS_30 0xE08C28
793
794#define mmTPC0_QM_ARB_MST_CRED_STS_31 0xE08C2C
795
796#define mmTPC0_QM_CGM_CFG 0xE08C70
797
798#define mmTPC0_QM_CGM_STS 0xE08C74
799
800#define mmTPC0_QM_CGM_CFG1 0xE08C78
801
802#define mmTPC0_QM_LOCAL_RANGE_BASE 0xE08C80
803
804#define mmTPC0_QM_LOCAL_RANGE_SIZE 0xE08C84
805
806#define mmTPC0_QM_CSMR_STRICT_PRIO_CFG 0xE08C90
807
808#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_1 0xE08C94
809
810#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_0 0xE08C98
811
812#define mmTPC0_QM_LBW_WR_RATE_LIM_CFG_1 0xE08C9C
813
814#define mmTPC0_QM_HBW_RD_RATE_LIM_CFG_0 0xE08CA0
815
816#define mmTPC0_QM_GLBL_AXCACHE 0xE08CA4
817
818#define mmTPC0_QM_IND_GW_APB_CFG 0xE08CB0
819
820#define mmTPC0_QM_IND_GW_APB_WDATA 0xE08CB4
821
822#define mmTPC0_QM_IND_GW_APB_RDATA 0xE08CB8
823
824#define mmTPC0_QM_IND_GW_APB_STATUS 0xE08CBC
825
826#define mmTPC0_QM_GLBL_ERR_ADDR_LO 0xE08CD0
827
828#define mmTPC0_QM_GLBL_ERR_ADDR_HI 0xE08CD4
829
830#define mmTPC0_QM_GLBL_ERR_WDATA 0xE08CD8
831
832#define mmTPC0_QM_GLBL_MEM_INIT_BUSY 0xE08D00
833
834#endif /* ASIC_REG_TPC0_QM_REGS_H_ */
835

source code of linux/drivers/accel/habanalabs/include/gaudi/asic_reg/tpc0_qm_regs.h