| 1 | /* SPDX-License-Identifier: GPL-2.0 |
| 2 | * |
| 3 | * Copyright 2016-2018 HabanaLabs, Ltd. |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | /************************************ |
| 9 | ** This is an auto-generated file ** |
| 10 | ** DO NOT EDIT BELOW ** |
| 11 | ************************************/ |
| 12 | |
| 13 | #ifndef ASIC_REG_MME2_QM_REGS_H_ |
| 14 | #define ASIC_REG_MME2_QM_REGS_H_ |
| 15 | |
| 16 | /* |
| 17 | ***************************************** |
| 18 | * MME2_QM (Prototype: QMAN) |
| 19 | ***************************************** |
| 20 | */ |
| 21 | |
| 22 | #define mmMME2_QM_GLBL_CFG0 0x168000 |
| 23 | |
| 24 | #define mmMME2_QM_GLBL_CFG1 0x168004 |
| 25 | |
| 26 | #define mmMME2_QM_GLBL_PROT 0x168008 |
| 27 | |
| 28 | #define mmMME2_QM_GLBL_ERR_CFG 0x16800C |
| 29 | |
| 30 | #define mmMME2_QM_GLBL_SECURE_PROPS_0 0x168010 |
| 31 | |
| 32 | #define mmMME2_QM_GLBL_SECURE_PROPS_1 0x168014 |
| 33 | |
| 34 | #define mmMME2_QM_GLBL_SECURE_PROPS_2 0x168018 |
| 35 | |
| 36 | #define mmMME2_QM_GLBL_SECURE_PROPS_3 0x16801C |
| 37 | |
| 38 | #define mmMME2_QM_GLBL_SECURE_PROPS_4 0x168020 |
| 39 | |
| 40 | #define mmMME2_QM_GLBL_NON_SECURE_PROPS_0 0x168024 |
| 41 | |
| 42 | #define mmMME2_QM_GLBL_NON_SECURE_PROPS_1 0x168028 |
| 43 | |
| 44 | #define mmMME2_QM_GLBL_NON_SECURE_PROPS_2 0x16802C |
| 45 | |
| 46 | #define mmMME2_QM_GLBL_NON_SECURE_PROPS_3 0x168030 |
| 47 | |
| 48 | #define mmMME2_QM_GLBL_NON_SECURE_PROPS_4 0x168034 |
| 49 | |
| 50 | #define mmMME2_QM_GLBL_STS0 0x168038 |
| 51 | |
| 52 | #define mmMME2_QM_GLBL_STS1_0 0x168040 |
| 53 | |
| 54 | #define mmMME2_QM_GLBL_STS1_1 0x168044 |
| 55 | |
| 56 | #define mmMME2_QM_GLBL_STS1_2 0x168048 |
| 57 | |
| 58 | #define mmMME2_QM_GLBL_STS1_3 0x16804C |
| 59 | |
| 60 | #define mmMME2_QM_GLBL_STS1_4 0x168050 |
| 61 | |
| 62 | #define mmMME2_QM_GLBL_MSG_EN_0 0x168054 |
| 63 | |
| 64 | #define mmMME2_QM_GLBL_MSG_EN_1 0x168058 |
| 65 | |
| 66 | #define mmMME2_QM_GLBL_MSG_EN_2 0x16805C |
| 67 | |
| 68 | #define mmMME2_QM_GLBL_MSG_EN_3 0x168060 |
| 69 | |
| 70 | #define mmMME2_QM_GLBL_MSG_EN_4 0x168068 |
| 71 | |
| 72 | #define mmMME2_QM_PQ_BASE_LO_0 0x168070 |
| 73 | |
| 74 | #define mmMME2_QM_PQ_BASE_LO_1 0x168074 |
| 75 | |
| 76 | #define mmMME2_QM_PQ_BASE_LO_2 0x168078 |
| 77 | |
| 78 | #define mmMME2_QM_PQ_BASE_LO_3 0x16807C |
| 79 | |
| 80 | #define mmMME2_QM_PQ_BASE_HI_0 0x168080 |
| 81 | |
| 82 | #define mmMME2_QM_PQ_BASE_HI_1 0x168084 |
| 83 | |
| 84 | #define mmMME2_QM_PQ_BASE_HI_2 0x168088 |
| 85 | |
| 86 | #define mmMME2_QM_PQ_BASE_HI_3 0x16808C |
| 87 | |
| 88 | #define mmMME2_QM_PQ_SIZE_0 0x168090 |
| 89 | |
| 90 | #define mmMME2_QM_PQ_SIZE_1 0x168094 |
| 91 | |
| 92 | #define mmMME2_QM_PQ_SIZE_2 0x168098 |
| 93 | |
| 94 | #define mmMME2_QM_PQ_SIZE_3 0x16809C |
| 95 | |
| 96 | #define mmMME2_QM_PQ_PI_0 0x1680A0 |
| 97 | |
| 98 | #define mmMME2_QM_PQ_PI_1 0x1680A4 |
| 99 | |
| 100 | #define mmMME2_QM_PQ_PI_2 0x1680A8 |
| 101 | |
| 102 | #define mmMME2_QM_PQ_PI_3 0x1680AC |
| 103 | |
| 104 | #define mmMME2_QM_PQ_CI_0 0x1680B0 |
| 105 | |
| 106 | #define mmMME2_QM_PQ_CI_1 0x1680B4 |
| 107 | |
| 108 | #define mmMME2_QM_PQ_CI_2 0x1680B8 |
| 109 | |
| 110 | #define mmMME2_QM_PQ_CI_3 0x1680BC |
| 111 | |
| 112 | #define mmMME2_QM_PQ_CFG0_0 0x1680C0 |
| 113 | |
| 114 | #define mmMME2_QM_PQ_CFG0_1 0x1680C4 |
| 115 | |
| 116 | #define mmMME2_QM_PQ_CFG0_2 0x1680C8 |
| 117 | |
| 118 | #define mmMME2_QM_PQ_CFG0_3 0x1680CC |
| 119 | |
| 120 | #define mmMME2_QM_PQ_CFG1_0 0x1680D0 |
| 121 | |
| 122 | #define mmMME2_QM_PQ_CFG1_1 0x1680D4 |
| 123 | |
| 124 | #define mmMME2_QM_PQ_CFG1_2 0x1680D8 |
| 125 | |
| 126 | #define mmMME2_QM_PQ_CFG1_3 0x1680DC |
| 127 | |
| 128 | #define mmMME2_QM_PQ_ARUSER_31_11_0 0x1680E0 |
| 129 | |
| 130 | #define mmMME2_QM_PQ_ARUSER_31_11_1 0x1680E4 |
| 131 | |
| 132 | #define mmMME2_QM_PQ_ARUSER_31_11_2 0x1680E8 |
| 133 | |
| 134 | #define mmMME2_QM_PQ_ARUSER_31_11_3 0x1680EC |
| 135 | |
| 136 | #define mmMME2_QM_PQ_STS0_0 0x1680F0 |
| 137 | |
| 138 | #define mmMME2_QM_PQ_STS0_1 0x1680F4 |
| 139 | |
| 140 | #define mmMME2_QM_PQ_STS0_2 0x1680F8 |
| 141 | |
| 142 | #define mmMME2_QM_PQ_STS0_3 0x1680FC |
| 143 | |
| 144 | #define mmMME2_QM_PQ_STS1_0 0x168100 |
| 145 | |
| 146 | #define mmMME2_QM_PQ_STS1_1 0x168104 |
| 147 | |
| 148 | #define mmMME2_QM_PQ_STS1_2 0x168108 |
| 149 | |
| 150 | #define mmMME2_QM_PQ_STS1_3 0x16810C |
| 151 | |
| 152 | #define mmMME2_QM_CQ_CFG0_0 0x168110 |
| 153 | |
| 154 | #define mmMME2_QM_CQ_CFG0_1 0x168114 |
| 155 | |
| 156 | #define mmMME2_QM_CQ_CFG0_2 0x168118 |
| 157 | |
| 158 | #define mmMME2_QM_CQ_CFG0_3 0x16811C |
| 159 | |
| 160 | #define mmMME2_QM_CQ_CFG0_4 0x168120 |
| 161 | |
| 162 | #define mmMME2_QM_CQ_CFG1_0 0x168124 |
| 163 | |
| 164 | #define mmMME2_QM_CQ_CFG1_1 0x168128 |
| 165 | |
| 166 | #define mmMME2_QM_CQ_CFG1_2 0x16812C |
| 167 | |
| 168 | #define mmMME2_QM_CQ_CFG1_3 0x168130 |
| 169 | |
| 170 | #define mmMME2_QM_CQ_CFG1_4 0x168134 |
| 171 | |
| 172 | #define mmMME2_QM_CQ_ARUSER_31_11_0 0x168138 |
| 173 | |
| 174 | #define mmMME2_QM_CQ_ARUSER_31_11_1 0x16813C |
| 175 | |
| 176 | #define mmMME2_QM_CQ_ARUSER_31_11_2 0x168140 |
| 177 | |
| 178 | #define mmMME2_QM_CQ_ARUSER_31_11_3 0x168144 |
| 179 | |
| 180 | #define mmMME2_QM_CQ_ARUSER_31_11_4 0x168148 |
| 181 | |
| 182 | #define mmMME2_QM_CQ_STS0_0 0x16814C |
| 183 | |
| 184 | #define mmMME2_QM_CQ_STS0_1 0x168150 |
| 185 | |
| 186 | #define mmMME2_QM_CQ_STS0_2 0x168154 |
| 187 | |
| 188 | #define mmMME2_QM_CQ_STS0_3 0x168158 |
| 189 | |
| 190 | #define mmMME2_QM_CQ_STS0_4 0x16815C |
| 191 | |
| 192 | #define mmMME2_QM_CQ_STS1_0 0x168160 |
| 193 | |
| 194 | #define mmMME2_QM_CQ_STS1_1 0x168164 |
| 195 | |
| 196 | #define mmMME2_QM_CQ_STS1_2 0x168168 |
| 197 | |
| 198 | #define mmMME2_QM_CQ_STS1_3 0x16816C |
| 199 | |
| 200 | #define mmMME2_QM_CQ_STS1_4 0x168170 |
| 201 | |
| 202 | #define mmMME2_QM_CQ_PTR_LO_0 0x168174 |
| 203 | |
| 204 | #define mmMME2_QM_CQ_PTR_HI_0 0x168178 |
| 205 | |
| 206 | #define mmMME2_QM_CQ_TSIZE_0 0x16817C |
| 207 | |
| 208 | #define mmMME2_QM_CQ_CTL_0 0x168180 |
| 209 | |
| 210 | #define mmMME2_QM_CQ_PTR_LO_1 0x168184 |
| 211 | |
| 212 | #define mmMME2_QM_CQ_PTR_HI_1 0x168188 |
| 213 | |
| 214 | #define mmMME2_QM_CQ_TSIZE_1 0x16818C |
| 215 | |
| 216 | #define mmMME2_QM_CQ_CTL_1 0x168190 |
| 217 | |
| 218 | #define mmMME2_QM_CQ_PTR_LO_2 0x168194 |
| 219 | |
| 220 | #define mmMME2_QM_CQ_PTR_HI_2 0x168198 |
| 221 | |
| 222 | #define mmMME2_QM_CQ_TSIZE_2 0x16819C |
| 223 | |
| 224 | #define mmMME2_QM_CQ_CTL_2 0x1681A0 |
| 225 | |
| 226 | #define mmMME2_QM_CQ_PTR_LO_3 0x1681A4 |
| 227 | |
| 228 | #define mmMME2_QM_CQ_PTR_HI_3 0x1681A8 |
| 229 | |
| 230 | #define mmMME2_QM_CQ_TSIZE_3 0x1681AC |
| 231 | |
| 232 | #define mmMME2_QM_CQ_CTL_3 0x1681B0 |
| 233 | |
| 234 | #define mmMME2_QM_CQ_PTR_LO_4 0x1681B4 |
| 235 | |
| 236 | #define mmMME2_QM_CQ_PTR_HI_4 0x1681B8 |
| 237 | |
| 238 | #define mmMME2_QM_CQ_TSIZE_4 0x1681BC |
| 239 | |
| 240 | #define mmMME2_QM_CQ_CTL_4 0x1681C0 |
| 241 | |
| 242 | #define mmMME2_QM_CQ_PTR_LO_STS_0 0x1681C4 |
| 243 | |
| 244 | #define mmMME2_QM_CQ_PTR_LO_STS_1 0x1681C8 |
| 245 | |
| 246 | #define mmMME2_QM_CQ_PTR_LO_STS_2 0x1681CC |
| 247 | |
| 248 | #define mmMME2_QM_CQ_PTR_LO_STS_3 0x1681D0 |
| 249 | |
| 250 | #define mmMME2_QM_CQ_PTR_LO_STS_4 0x1681D4 |
| 251 | |
| 252 | #define mmMME2_QM_CQ_PTR_HI_STS_0 0x1681D8 |
| 253 | |
| 254 | #define mmMME2_QM_CQ_PTR_HI_STS_1 0x1681DC |
| 255 | |
| 256 | #define mmMME2_QM_CQ_PTR_HI_STS_2 0x1681E0 |
| 257 | |
| 258 | #define mmMME2_QM_CQ_PTR_HI_STS_3 0x1681E4 |
| 259 | |
| 260 | #define mmMME2_QM_CQ_PTR_HI_STS_4 0x1681E8 |
| 261 | |
| 262 | #define mmMME2_QM_CQ_TSIZE_STS_0 0x1681EC |
| 263 | |
| 264 | #define mmMME2_QM_CQ_TSIZE_STS_1 0x1681F0 |
| 265 | |
| 266 | #define mmMME2_QM_CQ_TSIZE_STS_2 0x1681F4 |
| 267 | |
| 268 | #define mmMME2_QM_CQ_TSIZE_STS_3 0x1681F8 |
| 269 | |
| 270 | #define mmMME2_QM_CQ_TSIZE_STS_4 0x1681FC |
| 271 | |
| 272 | #define mmMME2_QM_CQ_CTL_STS_0 0x168200 |
| 273 | |
| 274 | #define mmMME2_QM_CQ_CTL_STS_1 0x168204 |
| 275 | |
| 276 | #define mmMME2_QM_CQ_CTL_STS_2 0x168208 |
| 277 | |
| 278 | #define mmMME2_QM_CQ_CTL_STS_3 0x16820C |
| 279 | |
| 280 | #define mmMME2_QM_CQ_CTL_STS_4 0x168210 |
| 281 | |
| 282 | #define mmMME2_QM_CQ_IFIFO_CNT_0 0x168214 |
| 283 | |
| 284 | #define mmMME2_QM_CQ_IFIFO_CNT_1 0x168218 |
| 285 | |
| 286 | #define mmMME2_QM_CQ_IFIFO_CNT_2 0x16821C |
| 287 | |
| 288 | #define mmMME2_QM_CQ_IFIFO_CNT_3 0x168220 |
| 289 | |
| 290 | #define mmMME2_QM_CQ_IFIFO_CNT_4 0x168224 |
| 291 | |
| 292 | #define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_0 0x168228 |
| 293 | |
| 294 | #define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_1 0x16822C |
| 295 | |
| 296 | #define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_2 0x168230 |
| 297 | |
| 298 | #define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_3 0x168234 |
| 299 | |
| 300 | #define mmMME2_QM_CP_MSG_BASE0_ADDR_LO_4 0x168238 |
| 301 | |
| 302 | #define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_0 0x16823C |
| 303 | |
| 304 | #define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_1 0x168240 |
| 305 | |
| 306 | #define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_2 0x168244 |
| 307 | |
| 308 | #define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_3 0x168248 |
| 309 | |
| 310 | #define mmMME2_QM_CP_MSG_BASE0_ADDR_HI_4 0x16824C |
| 311 | |
| 312 | #define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_0 0x168250 |
| 313 | |
| 314 | #define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_1 0x168254 |
| 315 | |
| 316 | #define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_2 0x168258 |
| 317 | |
| 318 | #define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_3 0x16825C |
| 319 | |
| 320 | #define mmMME2_QM_CP_MSG_BASE1_ADDR_LO_4 0x168260 |
| 321 | |
| 322 | #define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_0 0x168264 |
| 323 | |
| 324 | #define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_1 0x168268 |
| 325 | |
| 326 | #define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_2 0x16826C |
| 327 | |
| 328 | #define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_3 0x168270 |
| 329 | |
| 330 | #define mmMME2_QM_CP_MSG_BASE1_ADDR_HI_4 0x168274 |
| 331 | |
| 332 | #define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_0 0x168278 |
| 333 | |
| 334 | #define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_1 0x16827C |
| 335 | |
| 336 | #define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_2 0x168280 |
| 337 | |
| 338 | #define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_3 0x168284 |
| 339 | |
| 340 | #define mmMME2_QM_CP_MSG_BASE2_ADDR_LO_4 0x168288 |
| 341 | |
| 342 | #define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_0 0x16828C |
| 343 | |
| 344 | #define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_1 0x168290 |
| 345 | |
| 346 | #define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_2 0x168294 |
| 347 | |
| 348 | #define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_3 0x168298 |
| 349 | |
| 350 | #define mmMME2_QM_CP_MSG_BASE2_ADDR_HI_4 0x16829C |
| 351 | |
| 352 | #define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_0 0x1682A0 |
| 353 | |
| 354 | #define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_1 0x1682A4 |
| 355 | |
| 356 | #define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_2 0x1682A8 |
| 357 | |
| 358 | #define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_3 0x1682AC |
| 359 | |
| 360 | #define mmMME2_QM_CP_MSG_BASE3_ADDR_LO_4 0x1682B0 |
| 361 | |
| 362 | #define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_0 0x1682B4 |
| 363 | |
| 364 | #define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_1 0x1682B8 |
| 365 | |
| 366 | #define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_2 0x1682BC |
| 367 | |
| 368 | #define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_3 0x1682C0 |
| 369 | |
| 370 | #define mmMME2_QM_CP_MSG_BASE3_ADDR_HI_4 0x1682C4 |
| 371 | |
| 372 | #define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_0 0x1682C8 |
| 373 | |
| 374 | #define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_1 0x1682CC |
| 375 | |
| 376 | #define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_2 0x1682D0 |
| 377 | |
| 378 | #define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_3 0x1682D4 |
| 379 | |
| 380 | #define mmMME2_QM_CP_LDMA_TSIZE_OFFSET_4 0x1682D8 |
| 381 | |
| 382 | #define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x1682E0 |
| 383 | |
| 384 | #define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x1682E4 |
| 385 | |
| 386 | #define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x1682E8 |
| 387 | |
| 388 | #define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x1682EC |
| 389 | |
| 390 | #define mmMME2_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x1682F0 |
| 391 | |
| 392 | #define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x1682F4 |
| 393 | |
| 394 | #define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x1682F8 |
| 395 | |
| 396 | #define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x1682FC |
| 397 | |
| 398 | #define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x168300 |
| 399 | |
| 400 | #define mmMME2_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x168304 |
| 401 | |
| 402 | #define mmMME2_QM_CP_FENCE0_RDATA_0 0x168308 |
| 403 | |
| 404 | #define mmMME2_QM_CP_FENCE0_RDATA_1 0x16830C |
| 405 | |
| 406 | #define mmMME2_QM_CP_FENCE0_RDATA_2 0x168310 |
| 407 | |
| 408 | #define mmMME2_QM_CP_FENCE0_RDATA_3 0x168314 |
| 409 | |
| 410 | #define mmMME2_QM_CP_FENCE0_RDATA_4 0x168318 |
| 411 | |
| 412 | #define mmMME2_QM_CP_FENCE1_RDATA_0 0x16831C |
| 413 | |
| 414 | #define mmMME2_QM_CP_FENCE1_RDATA_1 0x168320 |
| 415 | |
| 416 | #define mmMME2_QM_CP_FENCE1_RDATA_2 0x168324 |
| 417 | |
| 418 | #define mmMME2_QM_CP_FENCE1_RDATA_3 0x168328 |
| 419 | |
| 420 | #define mmMME2_QM_CP_FENCE1_RDATA_4 0x16832C |
| 421 | |
| 422 | #define mmMME2_QM_CP_FENCE2_RDATA_0 0x168330 |
| 423 | |
| 424 | #define mmMME2_QM_CP_FENCE2_RDATA_1 0x168334 |
| 425 | |
| 426 | #define mmMME2_QM_CP_FENCE2_RDATA_2 0x168338 |
| 427 | |
| 428 | #define mmMME2_QM_CP_FENCE2_RDATA_3 0x16833C |
| 429 | |
| 430 | #define mmMME2_QM_CP_FENCE2_RDATA_4 0x168340 |
| 431 | |
| 432 | #define mmMME2_QM_CP_FENCE3_RDATA_0 0x168344 |
| 433 | |
| 434 | #define mmMME2_QM_CP_FENCE3_RDATA_1 0x168348 |
| 435 | |
| 436 | #define mmMME2_QM_CP_FENCE3_RDATA_2 0x16834C |
| 437 | |
| 438 | #define mmMME2_QM_CP_FENCE3_RDATA_3 0x168350 |
| 439 | |
| 440 | #define mmMME2_QM_CP_FENCE3_RDATA_4 0x168354 |
| 441 | |
| 442 | #define mmMME2_QM_CP_FENCE0_CNT_0 0x168358 |
| 443 | |
| 444 | #define mmMME2_QM_CP_FENCE0_CNT_1 0x16835C |
| 445 | |
| 446 | #define mmMME2_QM_CP_FENCE0_CNT_2 0x168360 |
| 447 | |
| 448 | #define mmMME2_QM_CP_FENCE0_CNT_3 0x168364 |
| 449 | |
| 450 | #define mmMME2_QM_CP_FENCE0_CNT_4 0x168368 |
| 451 | |
| 452 | #define mmMME2_QM_CP_FENCE1_CNT_0 0x16836C |
| 453 | |
| 454 | #define mmMME2_QM_CP_FENCE1_CNT_1 0x168370 |
| 455 | |
| 456 | #define mmMME2_QM_CP_FENCE1_CNT_2 0x168374 |
| 457 | |
| 458 | #define mmMME2_QM_CP_FENCE1_CNT_3 0x168378 |
| 459 | |
| 460 | #define mmMME2_QM_CP_FENCE1_CNT_4 0x16837C |
| 461 | |
| 462 | #define mmMME2_QM_CP_FENCE2_CNT_0 0x168380 |
| 463 | |
| 464 | #define mmMME2_QM_CP_FENCE2_CNT_1 0x168384 |
| 465 | |
| 466 | #define mmMME2_QM_CP_FENCE2_CNT_2 0x168388 |
| 467 | |
| 468 | #define mmMME2_QM_CP_FENCE2_CNT_3 0x16838C |
| 469 | |
| 470 | #define mmMME2_QM_CP_FENCE2_CNT_4 0x168390 |
| 471 | |
| 472 | #define mmMME2_QM_CP_FENCE3_CNT_0 0x168394 |
| 473 | |
| 474 | #define mmMME2_QM_CP_FENCE3_CNT_1 0x168398 |
| 475 | |
| 476 | #define mmMME2_QM_CP_FENCE3_CNT_2 0x16839C |
| 477 | |
| 478 | #define mmMME2_QM_CP_FENCE3_CNT_3 0x1683A0 |
| 479 | |
| 480 | #define mmMME2_QM_CP_FENCE3_CNT_4 0x1683A4 |
| 481 | |
| 482 | #define mmMME2_QM_CP_STS_0 0x1683A8 |
| 483 | |
| 484 | #define mmMME2_QM_CP_STS_1 0x1683AC |
| 485 | |
| 486 | #define mmMME2_QM_CP_STS_2 0x1683B0 |
| 487 | |
| 488 | #define mmMME2_QM_CP_STS_3 0x1683B4 |
| 489 | |
| 490 | #define mmMME2_QM_CP_STS_4 0x1683B8 |
| 491 | |
| 492 | #define mmMME2_QM_CP_CURRENT_INST_LO_0 0x1683BC |
| 493 | |
| 494 | #define mmMME2_QM_CP_CURRENT_INST_LO_1 0x1683C0 |
| 495 | |
| 496 | #define mmMME2_QM_CP_CURRENT_INST_LO_2 0x1683C4 |
| 497 | |
| 498 | #define mmMME2_QM_CP_CURRENT_INST_LO_3 0x1683C8 |
| 499 | |
| 500 | #define mmMME2_QM_CP_CURRENT_INST_LO_4 0x1683CC |
| 501 | |
| 502 | #define mmMME2_QM_CP_CURRENT_INST_HI_0 0x1683D0 |
| 503 | |
| 504 | #define mmMME2_QM_CP_CURRENT_INST_HI_1 0x1683D4 |
| 505 | |
| 506 | #define mmMME2_QM_CP_CURRENT_INST_HI_2 0x1683D8 |
| 507 | |
| 508 | #define mmMME2_QM_CP_CURRENT_INST_HI_3 0x1683DC |
| 509 | |
| 510 | #define mmMME2_QM_CP_CURRENT_INST_HI_4 0x1683E0 |
| 511 | |
| 512 | #define mmMME2_QM_CP_BARRIER_CFG_0 0x1683F4 |
| 513 | |
| 514 | #define mmMME2_QM_CP_BARRIER_CFG_1 0x1683F8 |
| 515 | |
| 516 | #define mmMME2_QM_CP_BARRIER_CFG_2 0x1683FC |
| 517 | |
| 518 | #define mmMME2_QM_CP_BARRIER_CFG_3 0x168400 |
| 519 | |
| 520 | #define mmMME2_QM_CP_BARRIER_CFG_4 0x168404 |
| 521 | |
| 522 | #define mmMME2_QM_CP_DBG_0_0 0x168408 |
| 523 | |
| 524 | #define mmMME2_QM_CP_DBG_0_1 0x16840C |
| 525 | |
| 526 | #define mmMME2_QM_CP_DBG_0_2 0x168410 |
| 527 | |
| 528 | #define mmMME2_QM_CP_DBG_0_3 0x168414 |
| 529 | |
| 530 | #define mmMME2_QM_CP_DBG_0_4 0x168418 |
| 531 | |
| 532 | #define mmMME2_QM_CP_ARUSER_31_11_0 0x16841C |
| 533 | |
| 534 | #define mmMME2_QM_CP_ARUSER_31_11_1 0x168420 |
| 535 | |
| 536 | #define mmMME2_QM_CP_ARUSER_31_11_2 0x168424 |
| 537 | |
| 538 | #define mmMME2_QM_CP_ARUSER_31_11_3 0x168428 |
| 539 | |
| 540 | #define mmMME2_QM_CP_ARUSER_31_11_4 0x16842C |
| 541 | |
| 542 | #define mmMME2_QM_CP_AWUSER_31_11_0 0x168430 |
| 543 | |
| 544 | #define mmMME2_QM_CP_AWUSER_31_11_1 0x168434 |
| 545 | |
| 546 | #define mmMME2_QM_CP_AWUSER_31_11_2 0x168438 |
| 547 | |
| 548 | #define mmMME2_QM_CP_AWUSER_31_11_3 0x16843C |
| 549 | |
| 550 | #define mmMME2_QM_CP_AWUSER_31_11_4 0x168440 |
| 551 | |
| 552 | #define mmMME2_QM_ARB_CFG_0 0x168A00 |
| 553 | |
| 554 | #define mmMME2_QM_ARB_CHOISE_Q_PUSH 0x168A04 |
| 555 | |
| 556 | #define mmMME2_QM_ARB_WRR_WEIGHT_0 0x168A08 |
| 557 | |
| 558 | #define mmMME2_QM_ARB_WRR_WEIGHT_1 0x168A0C |
| 559 | |
| 560 | #define mmMME2_QM_ARB_WRR_WEIGHT_2 0x168A10 |
| 561 | |
| 562 | #define mmMME2_QM_ARB_WRR_WEIGHT_3 0x168A14 |
| 563 | |
| 564 | #define mmMME2_QM_ARB_CFG_1 0x168A18 |
| 565 | |
| 566 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_0 0x168A20 |
| 567 | |
| 568 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_1 0x168A24 |
| 569 | |
| 570 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_2 0x168A28 |
| 571 | |
| 572 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_3 0x168A2C |
| 573 | |
| 574 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_4 0x168A30 |
| 575 | |
| 576 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_5 0x168A34 |
| 577 | |
| 578 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_6 0x168A38 |
| 579 | |
| 580 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_7 0x168A3C |
| 581 | |
| 582 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_8 0x168A40 |
| 583 | |
| 584 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_9 0x168A44 |
| 585 | |
| 586 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_10 0x168A48 |
| 587 | |
| 588 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_11 0x168A4C |
| 589 | |
| 590 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_12 0x168A50 |
| 591 | |
| 592 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_13 0x168A54 |
| 593 | |
| 594 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_14 0x168A58 |
| 595 | |
| 596 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_15 0x168A5C |
| 597 | |
| 598 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_16 0x168A60 |
| 599 | |
| 600 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_17 0x168A64 |
| 601 | |
| 602 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_18 0x168A68 |
| 603 | |
| 604 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_19 0x168A6C |
| 605 | |
| 606 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_20 0x168A70 |
| 607 | |
| 608 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_21 0x168A74 |
| 609 | |
| 610 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_22 0x168A78 |
| 611 | |
| 612 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_23 0x168A7C |
| 613 | |
| 614 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_24 0x168A80 |
| 615 | |
| 616 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_25 0x168A84 |
| 617 | |
| 618 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_26 0x168A88 |
| 619 | |
| 620 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_27 0x168A8C |
| 621 | |
| 622 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_28 0x168A90 |
| 623 | |
| 624 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_29 0x168A94 |
| 625 | |
| 626 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_30 0x168A98 |
| 627 | |
| 628 | #define mmMME2_QM_ARB_MST_AVAIL_CRED_31 0x168A9C |
| 629 | |
| 630 | #define mmMME2_QM_ARB_MST_CRED_INC 0x168AA0 |
| 631 | |
| 632 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x168AA4 |
| 633 | |
| 634 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x168AA8 |
| 635 | |
| 636 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x168AAC |
| 637 | |
| 638 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x168AB0 |
| 639 | |
| 640 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x168AB4 |
| 641 | |
| 642 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x168AB8 |
| 643 | |
| 644 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x168ABC |
| 645 | |
| 646 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x168AC0 |
| 647 | |
| 648 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x168AC4 |
| 649 | |
| 650 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x168AC8 |
| 651 | |
| 652 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x168ACC |
| 653 | |
| 654 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x168AD0 |
| 655 | |
| 656 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x168AD4 |
| 657 | |
| 658 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x168AD8 |
| 659 | |
| 660 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x168ADC |
| 661 | |
| 662 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x168AE0 |
| 663 | |
| 664 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x168AE4 |
| 665 | |
| 666 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x168AE8 |
| 667 | |
| 668 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x168AEC |
| 669 | |
| 670 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x168AF0 |
| 671 | |
| 672 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x168AF4 |
| 673 | |
| 674 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x168AF8 |
| 675 | |
| 676 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x168AFC |
| 677 | |
| 678 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x168B00 |
| 679 | |
| 680 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x168B04 |
| 681 | |
| 682 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x168B08 |
| 683 | |
| 684 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x168B0C |
| 685 | |
| 686 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x168B10 |
| 687 | |
| 688 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x168B14 |
| 689 | |
| 690 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x168B18 |
| 691 | |
| 692 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x168B1C |
| 693 | |
| 694 | #define mmMME2_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x168B20 |
| 695 | |
| 696 | #define mmMME2_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x168B28 |
| 697 | |
| 698 | #define mmMME2_QM_ARB_MST_SLAVE_EN 0x168B2C |
| 699 | |
| 700 | #define mmMME2_QM_ARB_MST_QUIET_PER 0x168B34 |
| 701 | |
| 702 | #define mmMME2_QM_ARB_SLV_CHOISE_WDT 0x168B38 |
| 703 | |
| 704 | #define mmMME2_QM_ARB_SLV_ID 0x168B3C |
| 705 | |
| 706 | #define mmMME2_QM_ARB_MSG_MAX_INFLIGHT 0x168B44 |
| 707 | |
| 708 | #define mmMME2_QM_ARB_MSG_AWUSER_31_11 0x168B48 |
| 709 | |
| 710 | #define mmMME2_QM_ARB_MSG_AWUSER_SEC_PROP 0x168B4C |
| 711 | |
| 712 | #define mmMME2_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x168B50 |
| 713 | |
| 714 | #define mmMME2_QM_ARB_BASE_LO 0x168B54 |
| 715 | |
| 716 | #define mmMME2_QM_ARB_BASE_HI 0x168B58 |
| 717 | |
| 718 | #define mmMME2_QM_ARB_STATE_STS 0x168B80 |
| 719 | |
| 720 | #define mmMME2_QM_ARB_CHOISE_FULLNESS_STS 0x168B84 |
| 721 | |
| 722 | #define mmMME2_QM_ARB_MSG_STS 0x168B88 |
| 723 | |
| 724 | #define mmMME2_QM_ARB_SLV_CHOISE_Q_HEAD 0x168B8C |
| 725 | |
| 726 | #define mmMME2_QM_ARB_ERR_CAUSE 0x168B9C |
| 727 | |
| 728 | #define mmMME2_QM_ARB_ERR_MSG_EN 0x168BA0 |
| 729 | |
| 730 | #define mmMME2_QM_ARB_ERR_STS_DRP 0x168BA8 |
| 731 | |
| 732 | #define mmMME2_QM_ARB_MST_CRED_STS_0 0x168BB0 |
| 733 | |
| 734 | #define mmMME2_QM_ARB_MST_CRED_STS_1 0x168BB4 |
| 735 | |
| 736 | #define mmMME2_QM_ARB_MST_CRED_STS_2 0x168BB8 |
| 737 | |
| 738 | #define mmMME2_QM_ARB_MST_CRED_STS_3 0x168BBC |
| 739 | |
| 740 | #define mmMME2_QM_ARB_MST_CRED_STS_4 0x168BC0 |
| 741 | |
| 742 | #define mmMME2_QM_ARB_MST_CRED_STS_5 0x168BC4 |
| 743 | |
| 744 | #define mmMME2_QM_ARB_MST_CRED_STS_6 0x168BC8 |
| 745 | |
| 746 | #define mmMME2_QM_ARB_MST_CRED_STS_7 0x168BCC |
| 747 | |
| 748 | #define mmMME2_QM_ARB_MST_CRED_STS_8 0x168BD0 |
| 749 | |
| 750 | #define mmMME2_QM_ARB_MST_CRED_STS_9 0x168BD4 |
| 751 | |
| 752 | #define mmMME2_QM_ARB_MST_CRED_STS_10 0x168BD8 |
| 753 | |
| 754 | #define mmMME2_QM_ARB_MST_CRED_STS_11 0x168BDC |
| 755 | |
| 756 | #define mmMME2_QM_ARB_MST_CRED_STS_12 0x168BE0 |
| 757 | |
| 758 | #define mmMME2_QM_ARB_MST_CRED_STS_13 0x168BE4 |
| 759 | |
| 760 | #define mmMME2_QM_ARB_MST_CRED_STS_14 0x168BE8 |
| 761 | |
| 762 | #define mmMME2_QM_ARB_MST_CRED_STS_15 0x168BEC |
| 763 | |
| 764 | #define mmMME2_QM_ARB_MST_CRED_STS_16 0x168BF0 |
| 765 | |
| 766 | #define mmMME2_QM_ARB_MST_CRED_STS_17 0x168BF4 |
| 767 | |
| 768 | #define mmMME2_QM_ARB_MST_CRED_STS_18 0x168BF8 |
| 769 | |
| 770 | #define mmMME2_QM_ARB_MST_CRED_STS_19 0x168BFC |
| 771 | |
| 772 | #define mmMME2_QM_ARB_MST_CRED_STS_20 0x168C00 |
| 773 | |
| 774 | #define mmMME2_QM_ARB_MST_CRED_STS_21 0x168C04 |
| 775 | |
| 776 | #define mmMME2_QM_ARB_MST_CRED_STS_22 0x168C08 |
| 777 | |
| 778 | #define mmMME2_QM_ARB_MST_CRED_STS_23 0x168C0C |
| 779 | |
| 780 | #define mmMME2_QM_ARB_MST_CRED_STS_24 0x168C10 |
| 781 | |
| 782 | #define mmMME2_QM_ARB_MST_CRED_STS_25 0x168C14 |
| 783 | |
| 784 | #define mmMME2_QM_ARB_MST_CRED_STS_26 0x168C18 |
| 785 | |
| 786 | #define mmMME2_QM_ARB_MST_CRED_STS_27 0x168C1C |
| 787 | |
| 788 | #define mmMME2_QM_ARB_MST_CRED_STS_28 0x168C20 |
| 789 | |
| 790 | #define mmMME2_QM_ARB_MST_CRED_STS_29 0x168C24 |
| 791 | |
| 792 | #define mmMME2_QM_ARB_MST_CRED_STS_30 0x168C28 |
| 793 | |
| 794 | #define mmMME2_QM_ARB_MST_CRED_STS_31 0x168C2C |
| 795 | |
| 796 | #define mmMME2_QM_CGM_CFG 0x168C70 |
| 797 | |
| 798 | #define mmMME2_QM_CGM_STS 0x168C74 |
| 799 | |
| 800 | #define mmMME2_QM_CGM_CFG1 0x168C78 |
| 801 | |
| 802 | #define mmMME2_QM_LOCAL_RANGE_BASE 0x168C80 |
| 803 | |
| 804 | #define mmMME2_QM_LOCAL_RANGE_SIZE 0x168C84 |
| 805 | |
| 806 | #define mmMME2_QM_CSMR_STRICT_PRIO_CFG 0x168C90 |
| 807 | |
| 808 | #define mmMME2_QM_HBW_RD_RATE_LIM_CFG_1 0x168C94 |
| 809 | |
| 810 | #define mmMME2_QM_LBW_WR_RATE_LIM_CFG_0 0x168C98 |
| 811 | |
| 812 | #define mmMME2_QM_LBW_WR_RATE_LIM_CFG_1 0x168C9C |
| 813 | |
| 814 | #define mmMME2_QM_HBW_RD_RATE_LIM_CFG_0 0x168CA0 |
| 815 | |
| 816 | #define mmMME2_QM_GLBL_AXCACHE 0x168CA4 |
| 817 | |
| 818 | #define mmMME2_QM_IND_GW_APB_CFG 0x168CB0 |
| 819 | |
| 820 | #define mmMME2_QM_IND_GW_APB_WDATA 0x168CB4 |
| 821 | |
| 822 | #define mmMME2_QM_IND_GW_APB_RDATA 0x168CB8 |
| 823 | |
| 824 | #define mmMME2_QM_IND_GW_APB_STATUS 0x168CBC |
| 825 | |
| 826 | #define mmMME2_QM_GLBL_ERR_ADDR_LO 0x168CD0 |
| 827 | |
| 828 | #define mmMME2_QM_GLBL_ERR_ADDR_HI 0x168CD4 |
| 829 | |
| 830 | #define mmMME2_QM_GLBL_ERR_WDATA 0x168CD8 |
| 831 | |
| 832 | #define mmMME2_QM_GLBL_MEM_INIT_BUSY 0x168D00 |
| 833 | |
| 834 | #endif /* ASIC_REG_MME2_QM_REGS_H_ */ |
| 835 | |